ufifocont.v

USBRTL电路的VHDL和Verilog代码

module Ufifocont (
		 mcclock,
		 usbclock,
		 syncreset,
		 mmcreset,
		 fifowr,
		 fiford,
		 fifowraddr,
		 fifordaddr,
		 fifordready,
		 fifowrready,
		 datapacketok,
		 datapacketnotok
		 );
  input         mcclock;
  input			 usbclock;
  input			 syncreset;
  input          mmcreset;
  input			 fifowr;
  input			 fiford;
  
  parameter		 DFFDEPTH = 32,
    			 DFFWIDTH = 8,
	    		 FULL = 32,
	    		 DFFADDRWIDTH = 5;	// 2^6 is 64
  
  output		 fifordready;
  output		 fifowrready;
  input			 datapacketok;
  input			 datapacketnotok;
  output[DFFADDRWIDTH-1:0] fifowraddr;
  output[DFFADDRWIDTH-1:0] fifordaddr;

  reg [DFFADDRWIDTH:0] wraddr,rdaddr,oldwraddr;
  wire			 full,empty;
  
  wire[DFFADDRWIDTH-1:0] fifowraddr = wraddr[DFFADDRWIDTH-1:0];
  wire[DFFADDRWIDTH-1:0] fifordaddr = rdaddr[DFFADDRWIDTH-1:0];

  always @(posedge usbclock)
    begin
      if (syncreset)
	begin
	  wraddr <= 'h0;
	  oldwraddr <= 'h0;
	end // if (syncreset)
      else
	begin
	  wraddr <= (fifowr) ? wraddr + 1'b1 : (datapacketnotok) ?
      oldwraddr : wraddr;
	  oldwraddr <= (datapacketok) ? wraddr : oldwraddr;
	end // else: !if(syncreset)
    end // always @ (posedge usbclock)
 
 always@(posedge mcclock)
	begin
	  if(mmcreset)
	    rdaddr <='h0;
      else 
		rdaddr <= (fiford) ? rdaddr +1'b1 :rdaddr;
   end
  
  assign empty = oldwraddr[DFFADDRWIDTH:0] == rdaddr[DFFADDRWIDTH:0];
  assign full = (wraddr[DFFADDRWIDTH-1:0] == rdaddr[DFFADDRWIDTH-1:0]) &&
                (wraddr[DFFADDRWIDTH] != rdaddr[DFFADDRWIDTH]);
  
  //wire fifordready =  full;
  //wire fifowrready = ~full;
   reg fifordready;
   reg fifowrready;
   always@(posedge mcclock)
      fifordready =  empty ? 0 : (full? 1: fifordready) ;
 
   always@(posedge usbclock)
      fifowrready = empty ? 1 : (full ? 0: fifowrready);
 // wire fifowrready =  ~fifordready;

  // synopsys translate_off
  always @(posedge usbclock)
    begin
      if (full && fifowr && !fiford)
	$write ("Error :****** %m fifo overrun at time %t\n",$time);
      if (empty && ~fifowr && fiford)
	$write ("Error :****** %m fifo underrun at time %t\n",$time);
    end // always @ (posedge usbclock)

  // synopsys translate_on

endmodule