stm_def.v

来自「USBRTL电路的VHDL和Verilog代码」· Verilog 代码 · 共 23 行

/******************************************
	Filename: 	stm_def.v 1.6
******************************************/

// 1/30/97 - these parameter names are included for simulation
// environment legacy only. i'm not using them anymore
// tc100 is tc100 it doesnt have a name associated that is used
// to invoke its task in the stimulus file tc100.v (formerly test_name.v)

parameter 
	CONFIG_TEST = 1,
	ISO_TEST = CONFIG_TEST + 1,
	ENDP1_TEST = ISO_TEST + 1,
	MEMRW_TEST = ENDP1_TEST + 1,
	MCU_TEST = MEMRW_TEST + 1,
	ENDP4_TEST = MCU_TEST + 1,
	CORE_CONFIG_TEST = ENDP4_TEST + 1,
	CORE_ENDP1_TEST = CORE_CONFIG_TEST + 1,
	CORE_ENDP2_TEST = CORE_ENDP1_TEST + 1,
	CORE_ENDP3_TEST = CORE_ENDP2_TEST + 1,
	CORE_ENDP4_TEST = CORE_ENDP3_TEST + 1,
  MAX_TESTS = 4096;  // thats a lot of tests, eh?