udevendpoints.v

USBRTL电路的VHDL和Verilog代码

/* 
This file includes the specific endpoint input and output
delcarations as well as the reg declarations for those
signals.
*/
// This next session describes our endpoints and is specific
// to each implementation
parameter	MAXENDPOINTS = 3;
parameter	MAXPACKET0 = 8;
parameter	MAXPACKET1 = 32;
parameter	MAXPACKET2 = 32;
parameter	MAXPACKET3 = 8;
// these next two have to cover all 16 endpoints to get ignore of invalid endpoints
// in gates, since 0 won't be default (ugh)
parameter	[15:0]	VALIDWRENDPOINTS = 16'h0003;	// endpoint 0 are valid for write 1
parameter	[15:0]	VALIDRDENDPOINTS = 16'h000c;	// endpoints 1, and 0 are valid for read f
parameter	[MAXENDPOINTS:0]	ISOENDPOINTS = 16'h0000;	// endpoints 3 and 1 are iso
parameter	[MAXENDPOINTS:0]	CONTROLENDPOINTS = 16'h0001;	// endpoint 0 is control 
parameter	REMOTEWAKEUP = 1'b0;
parameter	SELFPOWERED = 1'b0;