udevinouts.v

来自「USBRTL电路的VHDL和Verilog代码」· Verilog 代码 · 共 36 行

/* 
This file includes the specific endpoint input and output
declarations.
*/

output	[7:0]	currentalternatesetting;

// connections to endpoint0 - read/write
//output		endp0noncorecmd;
input	[7:0]	endp0rddata;
output	endp0rd;
input	endp0rdready;
input	endp0rdstall;
input	endp0wrready;
input	endp0wrstall;
output	endp0wr;

// connections to endpoint1 - read only
output	endp1wr;
input	endp1wrready;
//input	endp1wrstall;

// connections to endpoint2 - read only
output	endp2rd;
input	[7:0]	endp2rddata;
input	endp2rdready;
//input	endp2rdstall;

// connections to endpoint3 - read only
output	endp3rd;
input	[7:0]	endp3rddata;
input	endp3rdready;
//input	endp3rdstall;