shuaifa1.vhd

请先删除编译后的debug/release目录以减少压缩包大小

library  ieee;
use  ieee.std_logic_1164.all;
use  ieee.std_logic_arith.all;
use  ieee.std_logic_unsigned.all;
entity  shuaifa1  is
port(din:in  std_logic_vector(7  downto  0);
          qq:out  std_logic_vector(11  downto  0));
end  shuaifa1;
architecture  fun  of  shuaifa1  is
signal  num,yushu,jindu:integer;
begin
    num<=conv_integer(din);
p1:process(num)
    begin  
        If  num<51  then   qq(11  downto  8)<="0000";yushu<=num;
          elsif  num<102  then  qq(11  downto  8)<="0001";yushu<=num-51;
          elsif  num<153  then  qq(11  downto  8)<="0010";yushu<=num-102;
          elsif  num<204  then  qq(11  downto  8)<="0011";yushu<=num-153;
          elsif  num<255  then  qq(11  downto  8)<="0100";yushu<=num-204;
          else  qq(11  downto  8)<="0101";yushu<=0;
          end  if;
    end  process;
p2:process(yushu)
      begin
          if  yushu<5  then  qq(7  downto  4)<="0000";jindu<=yushu;
          elsif  yushu<10  then  qq(7  downto  4)<="0001";jindu<=yushu-5;
          elsif  yushu<15  then  qq(7  downto  4)<="0010";jindu<=yushu-10;
          elsif  yushu<20  then  qq(7  downto  4)<="0011";jindu<=yushu-15;
          elsif  yushu<25  then  qq(7  downto  4)<="0100";jindu<=yushu-20;
          elsif  yushu<30  then  qq(7  downto  4)<="0101";jindu<=yushu-25;
          elsif  yushu<35  then  qq(7  downto  4)<="0110";jindu<=yushu-30;
          elsif  yushu<40  then  qq(7  downto  4)<="0111";jindu<=yushu-35;
          elsif  yushu<45  then  qq(7  downto  4)<="1000";jindu<=yushu-40;
          else  qq(7  downto  4)<="1001";jindu<=yushu-45;
        end  if;
end  process;
p3:process(jindu)
      begin
      if  jindu=0  then
            qq(3  downto  0)<="0000";
      elsif  jindu=1  then  qq(3  downto  0)<="0010";
      elsif  jindu=2  then  qq(3  downto  0)<="0100";
      elsif  jindu=3  then  qq(3  downto  0)<="0110";
      else  qq(3  downto  0)<="1000";
  end  if;
end  process;    
end  fun;