adc.vhd

请先删除编译后的debug/release目录以减少压缩包大小

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY AD_CINT5 IS
  PORT(D:IN STD_LOGIC_vector(7 downto 0);
       CLK,EOC:IN STD_LOGIC;
       ALE,START:OUT STD_LOGIC;
       OE,ADDA:OUT STD_LOGIC;
       Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
            );
END AD_CINT5;
ARCHITECTURE BEHAV OF AD_CINT5 IS
TYPE STATES IS (ST0,ST1,ST2,ST3,ST4,ST5,ST6);
SIGNAL CURRENT_ST,NEXT_ST:STATES:=ST0;
SIGNAL REGL : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL LOCK: STD_LOGIC;
BEGIN
  ADDA<='1';
P:PROCESS(CLK)
   BEGIN
    IF (CLK'EVENT AND CLK='1')THEN
     CURRENT_ST<=NEXT_ST;
    END IF;
  END PROCESS P;
 P1:PROCESS(CURRENT_ST,EOC)
    BEGIN
   CASE CURRENT_ST IS
   WHEN ST0=>ALE<='0';START<='0';OE<='0';LOCK<='0';
     NEXT_ST<=ST1;
   WHEN ST1=>ALE<='1';START<='0';OE<='0';LOCK<='0';
     NEXT_ST<=ST2;
   WHEN ST2=>ALE<='0';START<='1';OE<='0';LOCK<='0';
     NEXT_ST<=ST3;
   WHEN ST3=>ALE<='0';START<='0';OE<='0';LOCK<='0';
    IF EOC='0' THEN
     NEXT_ST<=ST3;
    ELSE 
     NEXT_ST<=ST4;
    END IF; 
   WHEN ST4=>ALE<='0';START<='0';OE<='1';LOCK<='0';
     NEXT_ST<=ST5;
   WHEN ST5=>ALE<='0';START<='0';OE<='1';LOCK<='1';
     NEXT_ST<=ST6;
   WHEN ST6=>ALE<='0';START<='0';OE<='1';LOCK<='1';
     NEXT_ST<=ST0;
   WHEN OTHERS=>NEXT_ST<=ST0;
  END CASE;
 END PROCESS P1;
P2:PROCESS(LOCK)
    BEGIN
     IF LOCK='1'AND LOCK'EVENT THEN
        REGL<=D;
     END IF;
   END PROCESS P2;
     Q<=REGL;
 END BEHAV;