wx.vhd

来自「请先删除编译后的debug/release目录以减少压缩包大小」· VHDL 代码 · 共 22 行

LIBRARY IEEE;
USE IEEE.sTD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY WX IS
  PORT(CLK: IN  STD_LOGIC;
         Y:OUT  STD_LOGIC;
         Q:BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0));
END WX;
ARCHITECTURE a OF WX IS
BEGIN
PROCESS(CLK)
BEGIN
  IF RISING_EDGE(CLK) THEN
    IF Q="11" THEN      Q<="00";
    ELSE Q<=Q+1;
      IF Q="10" THEN Y<='1';      ELSE Y<='0';
      END IF;   END IF;     END IF;
END PROCESS;    
END a;