📄 xzq31.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY xzq31 IS
PORT( INPUT: IN STD_LOGIC_VECTOR(11 DOWNTO 0);
SES:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END xzq31;
ARCHITECTURE XZQ31JGT OF xzq31 IS
BEGIN
PROCESS(SES,INPUT)
BEGIN
CASE SES IS
WHEN "01"=>Q<=INPUT(11 DOWNTO 8);
WHEN "10"=>Q<=INPUT(7 DOWNTO 4);
WHEN "11"=>Q<=INPUT(3 DOWNTO 0);
WHEN OTHERS=>Q<="0000";
END CASE;
END PROCESS;
END XZQ31JGT;
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