📄 adc812.rpt
字号:
|lpm_add_sub:4038|altshift:carry_ext_latency_ffs|
|lpm_add_sub:4038|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:4039|
|lpm_add_sub:4039|addcore:adder|
|lpm_add_sub:4039|addcore:adder|addcore:adder0|
|lpm_add_sub:4039|altshift:result_ext_latency_ffs|
|lpm_add_sub:4039|altshift:carry_ext_latency_ffs|
|lpm_add_sub:4039|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:4124|
|lpm_add_sub:4124|addcore:adder|
|lpm_add_sub:4124|addcore:adder|addcore:adder0|
|lpm_add_sub:4124|altshift:result_ext_latency_ffs|
|lpm_add_sub:4124|altshift:carry_ext_latency_ffs|
|lpm_add_sub:4124|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:4125|
|lpm_add_sub:4125|addcore:adder|
|lpm_add_sub:4125|addcore:adder|addcore:adder0|
|lpm_add_sub:4125|altshift:result_ext_latency_ffs|
|lpm_add_sub:4125|altshift:carry_ext_latency_ffs|
|lpm_add_sub:4125|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:4205|
|lpm_add_sub:4205|addcore:adder|
|lpm_add_sub:4205|addcore:adder|addcore:adder0|
|lpm_add_sub:4205|altshift:result_ext_latency_ffs|
|lpm_add_sub:4205|altshift:carry_ext_latency_ffs|
|lpm_add_sub:4205|altshift:oflow_ext_latency_ffs|
Device-Specific Information: g:\lsm\adc812.rpt
adc812
***** Logic for device 'adc812' compiled without errors.
Device: EPM7096LC68-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
R R R R
~ ~ ~ ~ ~ E E E E
P P P P P V S S S S
I I I I I C E E V E E
N N N N N C R R C R R
0 0 0 G 0 0 I G G G G G V V C V V
0 0 0 N 0 0 N N N N N N E E I E E
6 7 8 D 9 1 T D D D D D D D O D D
-----------------------------------------------------_
/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |
~PIN005 | 10 60 | RESERVED
VCCIO | 11 59 | DOUT20
~PIN004 | 12 58 | GND
~PIN003 | 13 57 | DOUT10
INPUT7 | 14 56 | RESERVED
INPUT6 | 15 55 | RESERVED
GND | 16 54 | RESERVED
INPUT5 | 17 53 | VCCIO
INPUT4 | 18 EPM7096LC68-7 52 | RESERVED
INPUT3 | 19 51 | RESERVED
INPUT2 | 20 50 | RESERVED
VCCIO | 21 49 | RESERVED
INPUT1 | 22 48 | GND
~PIN002 | 23 47 | DOUT21
RESERVED | 24 46 | RESERVED
RESERVED | 25 45 | RESERVED
GND | 26 44 | RESERVED
|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|
------------------------------------------------------
R D R R V R I G V R D G R R R R V
E O E E C E N N C E O N E E E E C
S U S S C S P D C S U D S S S S C
E T E E I E U I E T E E E E I
R 2 R R O R T N R 2 R R R R O
V 3 V V V 0 T V 2 V V V V
E E E E E E E E E
D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: g:\lsm\adc812.rpt
adc812
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 10/16( 62%) 8/ 8(100%) 10/16( 62%) 15/36( 41%)
B: LC17 - LC32 16/16(100%) 8/ 8(100%) 14/16( 87%) 24/36( 66%)
C: LC33 - LC48 11/16( 68%) 2/ 8( 25%) 16/16(100%) 28/36( 77%)
D: LC49 - LC64 13/16( 81%) 1/ 8( 12%) 14/16( 87%) 30/36( 83%)
E: LC65 - LC80 16/16(100%) 1/ 8( 12%) 16/16(100%) 30/36( 83%)
F: LC81 - LC96 16/16(100%) 2/ 8( 25%) 16/16(100%) 29/36( 80%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 22/48 ( 45%)
Total logic cells used: 82/96 ( 85%)
Total shareable expanders used: 34/96 ( 35%)
Total Turbo logic cells used: 82/96 ( 85%)
Total shareable expanders not available (n/a): 52/96 ( 54%)
Average fan-in: 6.39
Total fan-in: 524
Total input pins required: 17
Total output pins required: 5
Total bidirectional pins required: 0
Total logic cells required: 82
Total flipflops required: 0
Total product terms required: 364
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 31
Synthesized logic cells: 20/ 96 ( 20%)
Device-Specific Information: g:\lsm\adc812.rpt
adc812
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
33 (33) (C) INPUT 0 0 0 0 0 0 16 INPUT0
22 (19) (B) INPUT 0 0 0 0 0 0 24 INPUT1
20 (21) (B) INPUT 0 0 0 0 0 0 24 INPUT2
19 (24) (B) INPUT 0 0 0 0 0 0 24 INPUT3
18 (25) (B) INPUT 0 0 0 0 0 0 16 INPUT4
17 (27) (B) INPUT 0 0 0 0 0 0 16 INPUT5
15 (29) (B) INPUT 0 0 0 0 0 0 16 INPUT6
14 (32) (B) INPUT 0 0 0 0 0 0 16 INPUT7
4 (16) (A) INPUT s 0 0 0 0 0 4 1 ~PIN001
23 (17) (B) INPUT s 0 0 0 0 0 4 1 ~PIN002
13 (1) (A) INPUT s 0 0 0 0 0 4 20 ~PIN003
12 (4) (A) INPUT s 0 0 0 0 0 4 20 ~PIN004
10 (6) (A) INPUT s 0 0 0 0 0 4 20 ~PIN005
9 (8) (A) INPUT s 0 0 0 0 0 4 16 ~PIN006
8 (9) (A) INPUT s 0 0 0 0 0 4 16 ~PIN007
7 (12) (A) INPUT s 0 0 0 0 0 4 20 ~PIN008
5 (14) (A) INPUT s 0 0 0 0 0 4 16 ~PIN009
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: g:\lsm\adc812.rpt
adc812
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
57 84 F OUTPUT t 0 0 0 0 0 0 0 DOUT10
59 86 F OUTPUT t 9 1 1 9 9 0 0 DOUT20
47 67 E OUTPUT t 9 1 1 9 9 0 0 DOUT21
37 51 D OUTPUT t 9 1 1 9 9 0 0 DOUT22
28 41 C OUTPUT t 9 1 1 9 9 0 0 DOUT23
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: g:\lsm\adc812.rpt
adc812
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 87 F SOFT t 0 0 0 2 0 0 8 |LPM_ADD_SUB:3034|addcore:adder|addcore:adder0|result_node1
(15) 29 B SOFT t 2 2 0 4 4 0 1 |LPM_ADD_SUB:3438|addcore:adder|addcore:adder0|gcp2
- 78 E SOFT t 0 0 0 3 1 0 1 |LPM_ADD_SUB:3438|addcore:adder|addcore:adder0|gs1
- 76 E SOFT t 0 0 0 3 1 0 3 |LPM_ADD_SUB:3438|addcore:adder|addcore:adder0|ps1
- 28 B SOFT t 1 0 1 4 1 1 7 |LPM_ADD_SUB:3438|addcore:adder|addcore:adder0|result_node0
- 20 B SOFT t 1 0 1 4 3 0 3 |LPM_ADD_SUB:3438|addcore:adder|addcore:adder0|result_node1
- 18 B SOFT t 3 2 1 4 4 0 2 |LPM_ADD_SUB:3438|addcore:adder|addcore:adder0|result_node2
(36) 49 D SOFT t 0 0 0 0 2 0 1 |LPM_ADD_SUB:3438|addcore:adder|addcore:adder0|result_node3
(10) 6 A SOFT t 1 0 1 4 0 0 4 |LPM_ADD_SUB:3438|datab_node0
- 34 C SOFT t 1 0 1 4 0 0 4 |LPM_ADD_SUB:3438|datab_node1
(30) 37 C SOFT t 1 0 1 4 0 0 2 |LPM_ADD_SUB:3438|datab_node2
(32) 35 C SOFT t 1 0 1 4 0 0 1 |LPM_ADD_SUB:3438|datab_node3
- 95 F SOFT t 0 0 0 0 2 1 6 |LPM_ADD_SUB:3439|addcore:adder|addcore:adder0|result_node1
- 91 F SOFT t 0 0 0 0 3 0 2 |LPM_ADD_SUB:3439|addcore:adder|addcore:adder0|result_node2
- 82 F SOFT t 0 0 0 0 4 0 1 |LPM_ADD_SUB:3439|addcore:adder|addcore:adder0|result_node3
(52) 75 E SOFT t 0 0 0 0 2 0 1 |LPM_ADD_SUB:3440|addcore:adder|addcore:adder0|gcp2
- 71 E SOFT t 0 0 0 0 2 1 4 |LPM_ADD_SUB:3440|addcore:adder|addcore:adder0|result_node2
- 42 C SOFT t 0 0 0 0 2 1 4 |LPM_ADD_SUB:3440|addcore:adder|addcore:adder0|result_node3
(14) 32 B SOFT t 2 2 0 4 4 0 1 |LPM_ADD_SUB:3531|addcore:adder|addcore:adder0|gcp2
- 79 E SOFT t 0 0 0 3 1 0 1 |LPM_ADD_SUB:3531|addcore:adder|addcore:adder0|gs1
(55) 80 E SOFT t 0 0 0 3 1 0 3 |LPM_ADD_SUB:3531|addcore:adder|addcore:adder0|ps1
- 31 B SOFT t 1 0 1 4 1 1 4 |LPM_ADD_SUB:3531|addcore:adder|addcore:adder0|result_node0
(20) 21 B SOFT t 1 0 1 4 3 1 7 |LPM_ADD_SUB:3531|addcore:adder|addcore:adder0|result_node1
- 22 B SOFT t 3 2 1 4 4 0 2 |LPM_ADD_SUB:3531|addcore:adder|addcore:adder0|result_node2
- 38 C SOFT t 1 0 1 4 0 0 4 |LPM_ADD_SUB:3531|datab_node0
(33) 33 C SOFT t 1 0 1 4 0 0 4 |LPM_ADD_SUB:3531|datab_node1
- 44 C SOFT t 1 0 1 4 0 0 2 |LPM_ADD_SUB:3531|datab_node2
(25) 45 C SOFT t 1 0 1 4 0 0 1 |LPM_ADD_SUB:3531|datab_node3
(44) 61 D SOFT t 0 0 0 0 2 0 1 |LPM_ADD_SUB:3532|addcore:adder|addcore:adder0|result_node3
(54) 77 E SOFT t 0 0 0 0 2 0 1 |LPM_ADD_SUB:3533|addcore:adder|addcore:adder0|gcp2
(50) 72 E SOFT t 0 0 0 0 2 1 5 |LPM_ADD_SUB:3533|addcore:adder|addcore:adder0|result_node2
(29) 40 C SOFT t 0 0 0 0 2 1 5 |LPM_ADD_SUB:3533|addcore:adder|addcore:adder0|result_node3
(23) 17 B SOFT t 2 2 0 4 4 0 1 |LPM_ADD_SUB:3618|addcore:adder|addcore:adder0|gcp2
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