ctrl.vhd

来自「采用MaxPlusII写的一个小时钟程序」· VHDL 代码 · 共 24 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY ctrl IS
	PORT(sysres,res,stst,cntclk:IN STD_ULOGIC;
			cnten:OUT STD_ULOGIC);
END ctrl;

ARCHITECTURE rtl OF ctrl IS
	SIGNAL enb1 :STD_ULOGIC;
BEGIN
	PROCESS(stst,sysres,res)
		BEGIN
			IF (sysres='1' OR res='1') THEN
				enb1<='0';
			ELSIF (stst 'EVENT AND stst='1') THEN
				enb1<= NOT enb1;
			END IF;
	END PROCESS;
	cnten<=enb1 AND cntclk;
END rtl;