📄 keyin.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY keyin IS
PORT(reset_sw,start_stop_sw,keyclk,clk:IN STD_ULOGIC;
res,stst:OUT STD_ULOGIC);
END keyin;
ARCHITECTURE rtl OF keyin IS
SIGNAL res0,res1,stst0,stst1:STD_LOGIC;
BEGIN
PROCESS(keyclk)
BEGIN
IF (keyclk 'EVENT AND keyclk='0') THEN
res1<=res0;
res0<=reset_sw;
stst1<=stst0;
stst0<=start_stop_sw;
END IF;
END PROCESS;
PROCESS(res0,res1,stst0,stst1)
BEGIN
res<=keyclk AND res0 AND (NOT res1);
stst<=keyclk AND stst0 AND (NOT stst1);
END PROCESS;
END rtl;
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