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📄 cnt1000.rpt

📁 采用MaxPlusII写的一个小时钟程序
💻 RPT
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   -      5     -    B    15       DFFE   +            2    1    0    4  q100029 (:26)
   -      6     -    B    08       DFFE   +            2    1    0    3  q100028 (:27)
   -      4     -    B    08       DFFE   +            2    1    0    4  q100027 (:28)
   -      2     -    B    08       DFFE   +            2    1    0    3  q100026 (:29)
   -      3     -    B    12       DFFE   +            2    1    0    3  q100025 (:30)
   -      1     -    B    12       DFFE   +            2    1    0    4  q100024 (:31)
   -      6     -    B    12       DFFE   +            2    1    0    5  q100023 (:32)
   -      8     -    B    18       DFFE   +            2    1    0    3  q100022 (:33)
   -      5     -    B    18       DFFE   +            2    1    0    4  q100021 (:34)
   -      4     -    B    19       DFFE   +            2    1    0    5  q100020 (:35)
   -      7     -    B    17       DFFE   +            2    1    0    3  q100019 (:36)
   -      5     -    B    17       DFFE   +            2    1    0    4  q100018 (:37)
   -      3     -    B    19       DFFE   +            2    1    0    5  q100017 (:38)
   -      2     -    B    17       DFFE   +            2    1    0    3  q100016 (:39)
   -      8     -    B    22       DFFE   +            2    1    0    4  q100015 (:40)
   -      6     -    B    22       DFFE   +            2    1    0    3  q100014 (:41)
   -      1     -    B    19       DFFE   +            2    1    0    4  q100013 (:42)
   -      4     -    B    09       DFFE   +            2    1    0    3  q100012 (:43)
   -      1     -    B    09       DFFE   +            2    1    0    4  q100011 (:44)
   -      2     -    B    09       DFFE   +            2    1    0    5  q100010 (:45)
   -      5     -    B    03       DFFE   +            2    1    0    3  q10009 (:46)
   -      7     -    B    03       DFFE   +            2    1    1    4  q10008 (:47)
   -      1     -    B    03       DFFE   +            2    1    1    5  q10007 (:48)
   -      8     -    B    05       DFFE   +            2    1    1    3  q10006 (:49)
   -      1     -    B    05       DFFE   +            2    1    1    4  q10005 (:50)
   -      4     -    B    05       DFFE   +            2    1    1    3  q10004 (:51)
   -      2     -    B    10       DFFE   +            2    1    1    4  q10003 (:52)
   -      6     -    B    10       DFFE   +            2    1    1    2  q10002 (:53)
   -      1     -    B    10       DFFE   +            2    1    1    3  q10001 (:54)
   -      5     -    B    10       DFFE   +            2    0    1    3  q10000 (:55)
   -      2     -    B    11        OR2    s           0    4    0    1  ~156~1
   -      3     -    B    11        OR2    s           0    4    0    1  ~156~2
   -      4     -    B    11        OR2    s           0    4    0    1  ~156~3
   -      5     -    B    11        OR2    s           0    4    0    1  ~156~4
   -      1     -    B    11        OR2    s           0    4    0    2  ~156~5
   -      3     -    B    18        OR2    s           0    3    0    1  ~156~6
   -      1     -    B    17        OR2    s           0    3    0    1  ~156~7
   -      3     -    B    22        OR2    s           0    4    0    1  ~156~8
   -      4     -    B    17        OR2    s           0    4    0    1  ~156~9
   -      1     -    B    18        OR2    s           0    4    0    2  ~156~10
   -      7     -    B    11        OR2                0    4    0    1  :456
   -      4     -    B    15        OR2                0    4    0    1  :465
   -      3     -    B    15        OR2                0    3    0    1  :474
   -      5     -    B    08        OR2                0    4    0    1  :483
   -      8     -    B    08        OR2                0    3    0    1  :492
   -      7     -    B    08        OR2                0    3    0    1  :501
   -      7     -    B    12        OR2                0    4    0    1  :510
   -      4     -    B    12        OR2                0    4    0    1  :519
   -      8     -    B    12        OR2                0    3    0    1  :528
   -      7     -    B    18        OR2                0    4    0    1  :537
   -      4     -    B    18        OR2                0    4    0    1  :546
   -      7     -    B    19        OR2                0    3    0    1  :555
   -      6     -    B    17        OR2                0    4    0    1  :564
   -      3     -    B    17        OR2                0    4    0    1  :573
   -      5     -    B    19        OR2                0    3    0    1  :582
   -      2     -    B    22        OR2                0    4    0    1  :591
   -      7     -    B    22        OR2                0    3    0    1  :600
   -      5     -    B    22        OR2                0    4    0    1  :609
   -      6     -    B    19        OR2                0    3    0    1  :618
   -      5     -    B    09        OR2                0    4    0    1  :627
   -      7     -    B    09        OR2                0    4    0    1  :636
   -      6     -    B    09        OR2                0    3    0    1  :645
   -      2     -    B    15        OR2    s           1    2    0   31  ~654~1
   -      4     -    B    03        OR2                0    4    0    1  :654
   -      8     -    B    03        OR2                0    4    0    1  :663
   -      6     -    B    03        OR2                0    3    0    1  :672
   -      7     -    B    05        OR2                0    4    0    1  :681
   -      5     -    B    05        OR2                0    3    0    1  :690
   -      3     -    B    05        OR2                0    4    0    1  :699
   -      8     -    B    10        OR2                0    3    0    1  :708
   -      4     -    B    10        OR2                0    4    0    1  :717
   -      3     -    B    10        OR2                0    3    0    1  :726
   -      6     -    B    15       AND2                1    1    1    0  :855


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:                   f:\study\vhdl\clock\cnt1000.rpt
cnt1000

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
B:      15/ 96( 15%)    19/ 48( 39%)    11/ 48( 22%)    0/16(  0%)      9/16( 56%)     0/16(  0%)
C:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                   f:\study\vhdl\clock\cnt1000.rpt
cnt1000

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       33         clk


Device-Specific Information:                   f:\study\vhdl\clock\cnt1000.rpt
cnt1000

** EQUATIONS **

clk      : INPUT;
en       : INPUT;
reset    : INPUT;

-- Node name is ':14' = 'ca' 
-- Equation name is 'ca', location is LC8_B15, type is buried.
ca       = DFFE( _EQ001, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ001 =  _LC7_B15
         #  ca & !en
         #  ca &  reset;

-- Node name is 'carry1' 
-- Equation name is 'carry1', type is output 
carry1   =  _LC6_B15;

-- Node name is 'q0' 
-- Equation name is 'q0', type is output 
q0       =  q10000;

-- Node name is 'q1' 
-- Equation name is 'q1', type is output 
q1       =  q10001;

-- Node name is 'q2' 
-- Equation name is 'q2', type is output 
q2       =  q10002;

-- Node name is 'q3' 
-- Equation name is 'q3', type is output 
q3       =  q10003;

-- Node name is 'q4' 
-- Equation name is 'q4', type is output 
q4       =  q10004;

-- Node name is 'q5' 
-- Equation name is 'q5', type is output 
q5       =  q10005;

-- Node name is 'q6' 
-- Equation name is 'q6', type is output 
q6       =  q10006;

-- Node name is 'q7' 
-- Equation name is 'q7', type is output 
q7       =  q10007;

-- Node name is 'q8' 
-- Equation name is 'q8', type is output 
q8       =  q10008;

-- Node name is ':55' = 'q10000' 
-- Equation name is 'q10000', location is LC5_B10, type is buried.
q10000   = DFFE( _EQ002, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ002 = !en &  q10000 & !reset
         #  en & !q10000 & !reset;

-- Node name is ':54' = 'q10001' 
-- Equation name is 'q10001', location is LC1_B10, type is buried.
q10001   = DFFE( _EQ003, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 =  _LC3_B10 & !reset
         # !en &  q10001 & !reset;

-- Node name is ':53' = 'q10002' 
-- Equation name is 'q10002', location is LC6_B10, type is buried.
q10002   = DFFE( _EQ004, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ004 =  _LC4_B10 & !reset
         # !en &  q10002 & !reset;

-- Node name is ':52' = 'q10003' 
-- Equation name is 'q10003', location is LC2_B10, type is buried.
q10003   = DFFE( _EQ005, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ005 =  _LC8_B10 & !reset
         # !en &  q10003 & !reset;

-- Node name is ':51' = 'q10004' 
-- Equation name is 'q10004', location is LC4_B5, type is buried.
q10004   = DFFE( _EQ006, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ006 =  _LC3_B5 & !reset
         # !en &  q10004 & !reset;

-- Node name is ':50' = 'q10005' 
-- Equation name is 'q10005', location is LC1_B5, type is buried.
q10005   = DFFE( _EQ007, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ007 =  _LC5_B5 & !reset
         # !en &  q10005 & !reset;

-- Node name is ':49' = 'q10006' 
-- Equation name is 'q10006', location is LC8_B5, type is buried.
q10006   = DFFE( _EQ008, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ008 =  _LC7_B5 & !reset
         # !en &  q10006 & !reset;

-- Node name is ':48' = 'q10007' 
-- Equation name is 'q10007', location is LC1_B3, type is buried.
q10007   = DFFE( _EQ009, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ009 =  _LC6_B3 & !reset
         # !en &  q10007 & !reset;

-- Node name is ':47' = 'q10008' 
-- Equation name is 'q10008', location is LC7_B3, type is buried.
q10008   = DFFE( _EQ010, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ010 =  _LC8_B3 & !reset
         # !en &  q10008 & !reset;

-- Node name is ':46' = 'q10009' 
-- Equation name is 'q10009', location is LC5_B3, type is buried.
q10009   = DFFE( _EQ011, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ011 =  _LC4_B3 & !reset
         # !en &  q10009 & !reset;

-- Node name is ':45' = 'q100010' 
-- Equation name is 'q100010', location is LC2_B9, type is buried.
q100010  = DFFE( _EQ012, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ012 =  _LC6_B9 & !reset
         # !en &  q100010 & !reset;

-- Node name is ':44' = 'q100011' 
-- Equation name is 'q100011', location is LC1_B9, type is buried.
q100011  = DFFE( _EQ013, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ013 =  _LC7_B9 & !reset
         # !en &  q100011 & !reset;

-- Node name is ':43' = 'q100012' 
-- Equation name is 'q100012', location is LC4_B9, type is buried.
q100012  = DFFE( _EQ014, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ014 =  _LC5_B9 & !reset
         # !en &  q100012 & !reset;

-- Node name is ':42' = 'q100013' 
-- Equation name is 'q100013', location is LC1_B19, type is buried.
q100013  = DFFE( _EQ015, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ015 =  _LC6_B19 & !reset
         # !en &  q100013 & !reset;

-- Node name is ':41' = 'q100014' 
-- Equation name is 'q100014', location is LC6_B22, type is buried.
q100014  = DFFE( _EQ016, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ016 =  _LC5_B22 & !reset
         # !en &  q100014 & !reset;

-- Node name is ':40' = 'q100015' 
-- Equation name is 'q100015', location is LC8_B22, type is buried.
q100015  = DFFE( _EQ017, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ017 =  _LC7_B22 & !reset
         # !en &  q100015 & !reset;

-- Node name is ':39' = 'q100016' 
-- Equation name is 'q100016', location is LC2_B17, type is buried.

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