ten.txt

用VHDL语言写的时钟程序。采用模块化编程。可在EPM7128芯片上下载。编译环境可用Maxplus或Quartus。

--10分频电路
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;


entity ten is      -----------------------------------10分频电路
	port( reset: in std_logic;    ----------------复位信号
          cp100:   in   std_logic;    ----------------输入时钟 
          startstopctr:in std_logic;  ----------------停止控制信号
          dao:in std_logic;      ---------------------正/倒记时控制信号
	      msecond:out  integer range 0 to 9;    --秒表输出
          cp1:    out  std_logic); -------------------下级时钟
end ten;

architecture mse of ten is
signal mcounter:integer range 0 to 9;
signal cpone: std_logic;
begin 
    process(cp100)
       begin
       if(reset='0' and startstopctr='0' and dao='1') then --判断是否清零
       mcounter<=0;
       msecond<=0;
       cpone<='0';
       else
         if(cp100'event and cp100='0')
         then
           if(startstopctr='1') then  ------------------------判断是否开启
              if(mcounter=9) then
                 mcounter<=0;
              else mcounter<=mcounter+1;
              end if;
              if(mcounter<=3 or mcounter=9) then
                 cpone<='0';
              else cpone<='1';
              end if;
           end if;
         end if;
      cp1<=cpone;
    end if;
    if(dao='1') then     --------------------------------判断是正记时
        msecond<=mcounter;
      else msecond<=9-mcounter;   ----------------------判断是倒记时
    end if;
    end process;
end mse;