six.txt

来自「用VHDL语言写的时钟程序。采用模块化编程。可在EPM7128芯片上下载。编译环」· 文本 代码 · 共 47 行

--6分频电路

 library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;


entity six is    ------------------------------------6分频电路
	port( reset: in std_logic;     --------------复位信号
          cp1:   in   std_logic;  -------------------输入时钟
          startstopctr:in std_logic;    -------------停止控制信号
          dao:in std_logic;      --------------------正/倒记时控制信号
	  second:out  integer range 0 to 9; ---------秒表输出
          minute:out  std_logic);  ------------------下级时钟
end six;

architecture se of six is
signal counter:integer range 0 to 9;
begin 
    process(cp1)
       begin
       if(reset='0' and startstopctr='0' and dao='1') then --判断是否清零
       counter<=0;
       second<=0;
       minute<='0';
       else
         if(cp1'event and cp1='0')
         then
            if(counter=5) then
               counter<=0;
            else counter<=counter+1;
            end if;
            if(counter<=1 or counter=5) then
                 minute<='0';
              else minute<='1';
            end if;
         end if;
       end if;
       if(dao='1') then   ---------------------------判断是正记时
          second<=counter;
         else          ------------------------------判断是倒记时
          second<=5-counter;
       end if;
       end process;
end se;