ding.txt

用VHDL语言写的时钟程序。采用模块化编程。可在EPM7128芯片上下载。编译环境可用Maxplus或Quartus。

--顶层文件
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;


entity ding is                             
port(
     resetin: in std_logic;   --------------------复位按键
     startstopin: in std_logic;    ---------------启停案件
     clk: in std_logic;     ----------------------1M时钟
     dao:in std_logic;       ---------------------正/到控制信号
     man:in std_logic;       ---------------------速度调整控制信号
     aout,bout,cout,dout,eout,fout: out std_logic_vector(0 to 6);
                                                 --控制数码管的信号
     hour: out std_logic);   ----------------------无用信号
end ding;

architecture yong of ding is
component shan                                   --元件例化
     port(
          clk:  in  std_logic;
          cp100:out std_logic);
end component;

component ten
     port(reset: in std_logic;
          cp100:   in   std_logic;
          startstopctr:in std_logic;
          dao:in std_logic;
	      msecond:out  integer range 0 to 9;
          cp1:    out  std_logic);
end component;

  component six
  	port( reset: in std_logic;
          cp1:   in   std_logic;
          startstopctr:in std_logic;
          dao:in std_logic;
	      second:out  integer range 0 to 9;
          minute:out  std_logic);
     end component;
 
component contr
   port (cp100:in std_logic;
         startstop: in std_logic;
         reset:in std_logic;
         dao:in std_logic;
         startstopctr: out std_logic;
         kan:     out std_logic);
end component;

component zhuanhuan 
port(
     nm10: in integer range 0 to 9;
     nm2: out std_logic_vector(0 to 6));
end component;

--声明传递各元件之间信息的信号
 signal trans1,trans2,trans3,trans4,trans5,trans6,trans7,trans8 :std_logic;
 signal a,b,c,d,e,f:integer range 0 to 9;
 signal x:integer range 0 to 9;
 signal y:std_logic_vector(0 to 6);
 signal huan:integer range 0 to 9;
 signal cpzhuan,cpting:std_logic;
--signal am,bm,cm,dm,em,fm:std_logic_vector(0 to 6);

 
 
--调用元件

   begin
     u1:contr port map(trans2,startstopin,resetin,dao,trans1,trans8);
     u2:shan  port map(clk,trans2);
     u3:ten   port map(resetin,trans2,trans1,dao,a,trans3);
     u4:ten   port map(resetin,cpting,trans1,dao,b,trans4);
     u5:ten   port map(resetin,trans4,trans1,dao,c,trans5);
     u6:six port map(resetin,cpzhuan,trans1,dao,d,trans6);
     u7:ten   port map(resetin,trans6,trans1,dao,e,trans7);
     u8:six port map(resetin,trans7,trans1,dao,f,hour);
     u9:zhuanhuan port map(x,y);

--扫频电路
  process(clk)
     begin
      if(clk'event and clk='0') then
         if(huan>=5) then
           huan<=0;
         else huan<=huan+1;
       end if;
       if(trans8='0')then  --------------------判断是否暗走
         if(huan=0) then 
          x<=a;
          aout<=y;
           elsif(huan=1) then 
            x<=b;
            bout<=y;                          --让转换电路分时处理
           elsif(huan=2) then                 --秒表的6个输出
            x<=c;
            cout<=y;
          elsif(huan=3) then 
            x<=d;
            dout<=y;
          elsif(huan=4) then 
            x<=e;
            eout<=y;
          else  
            x<=f;
            fout<=y;
         end if;
       end if;
      if(dao='0' and resetin='0') then
        if(man='1') then
         cpzhuan<=trans2;
         cpting<='1';
        else
         cpzhuan<=trans3;
         cpting<='1';
        end if;
        else
          cpzhuan<=trans5;
          cpting<=trans3;
      end if;
      end if;
   end process;
 
 
   end yong;