zhuanhuan.txt

用VHDL语言写的时钟程序。采用模块化编程。可在EPM7128芯片上下载。编译环境可用Maxplus或Quartus。

--转换电路，把数字0-9转换成控制数码管的高低电平信号


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;



entity zhuanhuan is                            
port(
     nm10: in integer range 0 to 9;  -------------输入是数字0-9
     nm2 : out std_logic_vector(0 to 6));   --输出是7位数组，控制7段数码管
end zhuanhuan;

architecture using of zhuanhuan is
begin
  process(nm10)
  begin
   case nm10 is
      when 0=>nm2<="1111110";
      when 1=>nm2<="0110000";
      when 2=>nm2<="1101101";
      when 3=>nm2<="1111001";
      when 4=>nm2<="0110011";
      when 5=>nm2<="1011011";
      when 6=>nm2<="1011111";
      when 7=>nm2<="1110000";
      when 8=>nm2<="1111111";
      when 9=>nm2<="1111011";
   end case;
  end process;
end using;