gold.txt

SRL16是Virtex器件中的一个移位寄存器查找表。它有4个输入用来选择输出序列的长度。使用XCV50-6器件实现

--SRL16是Virtex器件中的一个移位寄存器查找表。它有4个输入用来选择输出序列的长度。使用XCV50-6器件实现，共占用5个Slice。
library ieee;
use ieee.std_logic_1164.all;
entity LFSR_A is
generic (cycleA0:integer:=26; 
         cycleA3:integer:=4;
         width:integer:=1);     
   port (clk:in std_logic;     
         enable:in std_logic;
         fill_en:in std_logic;
         new_fill:in std_logic_vector(width-1 downto 0);    
         delayA0:out std_logic_vector(width-1 downto 0));
end LFSR_A;

architecture LFSR_A_ARCH of LFSR_A is
signal data_in_A:std_logic_vector(width-1 downto 0);    
signal delayA3:std_logic_vector(width-1 downto 0);
signal delayA0_int:std_logic_vector(width-1 downto 0);
type my_type is array (0 to cycleA0-1) of    
std_logic_vector(width-1 downto 0);
signal int_sigA0:my_type;
type my_type2 is array (0 to cycleA3-1) of
std_logic_vector(width-1 downto 0);
signal int_sigA3:my_type2;

begin
main:process(clk)
begin
if clk’event and clk=’1’ then
  if (enable=’1’) then
    int_sigA0<=data_in_A&int_sigA0(0 to cycleA0-2);
    int_sigA3<=data_in_A&int_sigA3(0 to cycleA3-2);
  end if;
  if (fill_en=’0’) then data_in_A<=delayA3 xor delayA0_int;
  else data_in_A<=new_fill;
  end if;
end if;
end process main;

delayA0_int<=int_sigA0(cycleA0-1);
delayA3_int<=int_sigA3(cycleA3-1);
delayA0<=delayA0_int;
end LFSR_A_ARCH;



library ieee;
use ieee.std_logic_1164.all;
entity LFSR_B is
generic (cycleB0:integer:=26;
         cycleB20:integer:=21;
         width:integer:=1);
    port (clk:in std_logic;
          enable:in std_logic;
          fill_en:in std_logic;
          new_fill:in std_logic_vector(width-1 downto 0);
          delayB0:out std_logic_vector(width-1 downto 0));
end LFSR_B;

architecture LFSR_B_ARCH of LFSR_B is
signal data_in_B:std_logic_vector(width-1 downto 0);
signal delayB20:std_logic_vector(width-1 downto 0);
signal delayB0_int:std_logic_vector(width-1 downto 0);
type my_type is array (0 to cycleA0-1) of
std_logic_vector(width-1 downto 0);
signal int_sigB0:my_type;
type my_type2 is array (0 to cycleA3-1) of
std_logic_vector(width-1 downto 0);
signal int_sigB20:my_type2;

begin
main:process(clk)
begin
if clk’event and clk=’1’ then
  if (enable=’1’) then
    int_sigB0<=data_in_B&int_sigB0(0 to cycleA0-2);
    int_sigB20<=data_in_B&int_sigB20(0 to cycleA3-2);
  end if;
  if (fill_en=’0’) then data_in_B<=delayB20 xor delayB0_int;
  else data_in_B<=new_fill;
  end if;
end if;
end process main;

delayB0_int<=int_sigB0(cycleB0-1);
delayB20_int<=int_sigB20(cycleB20-1);
delayB0<=delayB0_int;
end LFSR_B_ARCH;



library ieee;
use ieee.std_logic_1164.all;
entity gold_code is
generic (width:integer:=1);
   port (clk:in std_logic;
         enable:in std_logic;
         fill_en_A:in std_logic;
         fill_en_B:in std_logic;
         rst:in std_logic;
         new_fill_A:in std_logic_vector(width-1 downto 0);
         new_fill_B:in std_logic_vector(width-1 downto 0);
         Gold_Code:out std_logic_vector(width-1 downto 0));
end gold_code;

architecture gold_code_arch of gold_code is
component LFSR_A port
(clk:in std_logic;
 enable:in std_logic;
 fill_en:in std_logic;
 new_fill:in std_logic_vector(width-1 downto 0);
delayA0:out std_logic_vector(width-1 downto 0));
end component;

component LFSR_B port
(clk:in std_logic;
 enable:in std_logic;
 fill_en:in std_logic;
 new_fill:in std_logic_vector(width-1 downto 0);
delayB0:out std_logic_vector(width-1 downto 0));
end component;

signal delatA_top:std_logic_vector(width-1 downto 0);
signal delatB_top:std_logic_vector(width-1 downto 0);

begin
U0:LFSR_A port map(clk=>clock,enable=>enable,
                   fill_en=>fill_en_A,
                   new_fill=>new_fill_A,
                   delayA0=>delayA_top);

U1:LFSR_B port map(clk=>clock,enable=>enable,
                   fill_en=>fill_en_B,
                   new_fill=>new_fill_B,
                   delayB0=>delayB_top);
gold_code<=delayB_top xor delayA_top;
end gold_code_arch;