rx_test_harness.v

来自「altera fpga 和ts201的linkport接口设计」· Verilog 代码 · 共 245 行

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//---------------------------------------------------------------------------
// Test harness for ADI link port
//---------------------------------------------------------------------------
`timescale 1ps/1ps

module rx_tb ();

  reg clk;
  reg rst_n;

  reg [3:0] lp_data;
  wire 	    lp_clk;

  reg 	    rvere;

  reg 	    rdreq;
  wire 	    empty;
  wire [32:0] rdata;
  wire 	      acko;
  reg 	      bcmpi_n;

  integer seed;
  integer i;

  reg 	  lp_clk_src;
  reg [3:0] lp_data_src;
  reg 	    lp_clk_mux;
  reg [7:0] cksum;
  reg 	    send_cksum;
  reg 	    send_dummy;
  reg 	    force_error;
  
  parameter DEVICE = "Stratix";

  // worst case clk 200MHz
  `define local_clk_period 5000
  // Drive local clk source
  initial begin
    clk = 1'b0;
    while (1) #(`local_clk_period/2) clk = ~clk;
  end

  // lp_clk 500MHz
  `define lp_clk_period 2000
  // Drive lp_clk source
  initial begin
    lp_clk_src = 1'b0;
    while (1) #(`lp_clk_period/2) lp_clk_src = ~lp_clk_src;
  end

  initial
    begin
      seed = 1;
      rst_n = 1'b0;
      lp_clk_mux = 1'b0;
      rdreq = 1'b0;
      rvere = 1'b1;
      bcmpi_n = 1'b1;
      cksum = 8'b0;
      send_cksum = 1'b0;
      send_dummy = 1'b0;
      force_error = 1'b0;
      repeat (5) @(posedge clk);
      rst_n = 1'b1;
      repeat (3) @(posedge clk);

      @(negedge lp_clk_src);
      fork
	lp_traffic;

	begin
	  repeat (7) @(posedge lp_clk);
	  bcmpi_n = 1'b0;
	  repeat (4) @(posedge lp_clk);
	  bcmpi_n = 1'b1;
	end
      join
      repeat (30) @(negedge lp_clk_src);

      // with forced error
      @(negedge lp_clk_src);
      force_error = 1'b1;
      lp_traffic;
      force_error = 1'b0;

      repeat (20) @(negedge lp_clk_src);

      @(negedge lp_clk_src);
      for (i=1; i<5; i=i+1)
	lp_traffic;

      repeat (5) @(posedge clk);
      
      @(negedge lp_clk_src);
      for (i=1; i<5; i=i+1)
	lp_traffic;

      repeat (4) @(posedge clk);
      
      @(negedge lp_clk_src);
      for (i=1; i<5; i=i+1)
	lp_traffic;

      repeat (3) @(posedge clk);
      
      @(negedge lp_clk_src);
      for (i=1; i<5; i=i+1)
	lp_traffic;

      repeat (2) @(posedge clk);
      
      @(negedge lp_clk_src);
      for (i=1; i<5; i=i+1)
	lp_traffic;

      repeat (1) @(posedge clk);
      
      @(negedge lp_clk_src);
      for (i=1; i<5; i=i+1)
	lp_traffic;

      @(negedge lp_clk_src);
      for (i=1; i<5; i=i+1)
	lp_traffic;

      repeat (5) @(posedge clk);
      
      $finish;
    end

  always
    begin
      repeat (5) @(posedge clk);
      while (empty)
	@(posedge clk);
      @(posedge clk);
      rdreq = 1'b1;
      while (~empty)
	@(posedge clk);
      rdreq = 1'b0;
    end
  
  always @(lp_clk_src)
  begin
    #(`lp_clk_period/4);
    lp_data_src = $random(seed);
  end

  reg [3:0] cksum_src;
  always @(posedge send_cksum)
  begin
    cksum_src <= force_error ? ~cksum[3:0] : cksum[3:0];
    @(posedge lp_clk) #(`lp_clk_period/4);
    cksum_src <= force_error ? ~cksum[7:4] : cksum[7:4];
  end
  
  always @(send_dummy or send_cksum or cksum_src or lp_clk_mux or lp_data_src)
    if (send_dummy)
      lp_data <= 4'b0;
    else if (send_cksum)
      lp_data <= cksum_src;
    else if (lp_clk_mux)
      lp_data <= lp_data_src;
    else
      lp_data <= 4'b0;

  assign lp_clk = lp_clk_mux ? lp_clk_src : 1'b0;

//---------------------------------------------------------------------------
  // *** Write this properly to generate 4 words, calculate checksums
  // *** and transmit them
//---------------------------------------------------------------------------
  task lp_traffic;
    reg [3:0] cksum_nibble;
    begin
      lp_clk_mux <= 1'b1;
      repeat (16)
      begin
	@(posedge lp_clk_src);
	cksum_nibble <= lp_data;
	@(negedge lp_clk_src);
	cksum <= cksum + {lp_data, cksum_nibble};
      end
      #(`lp_clk_period/4);
      if (rvere)
      begin
	send_cksum <= 1'b1;
	@(posedge lp_clk_src);
	@(negedge lp_clk_src) #(`lp_clk_period/4);
	send_cksum <= 1'b0;
	send_dummy <= 1'b1;
	@(posedge lp_clk_src);
	@(negedge lp_clk_src) #(`lp_clk_period/4);
	send_dummy <= 1'b0;
      end
      lp_clk_mux <= 1'b0;
      cksum <= 8'b0;
    end
  endtask
    
//---------------------------------------------------------------------------
//---------------------------------------------------------------------------
  lp_rx #(DEVICE) dut (.clk		(clk),
		       .rst_n		(rst_n),

		       .datain		(lp_data),
		       .inclock		(lp_clk),
		       .inclock_en	(1'b1),
		       
		       .acko		(acko),
		       .bcmpi_n		(bcmpi_n),

		       .rvere		(rvere),
		       .rcser		(rcser),
		       
		       .rdreq		(rdreq),
		       .empty		(empty),
		       .rdata		(rdata)
		       );

endmodule