tx_test_harness.v

来自「altera fpga 和ts201的linkport接口设计」· Verilog 代码 · 共 223 行

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//---------------------------------------------------------------------------
// Test harness for ADI link port
//---------------------------------------------------------------------------
`timescale 1ps/1ps

module tx_tb ();

  reg clk;
  reg clk270;
  reg clk4;
  reg rst_n;

  integer seed;

  reg 	  tvere;
  
  reg 	     tx_wr;
  reg [32:0] tx_wdata;
  wire [3:0] tx_wrused;
  wire 	     tx_wrfull;
  reg 	     acki;
  wire 	     bcmpo_n;

  wire 	    clk_out;
  wire [3:0] data_out;

  integer    test;
  integer    delay;

  reg [7:0]  expect_check;

  parameter  DEVICE	= "Stratix";  
  
  `define local_clk_period 10000
  // Drive local clk source
  initial
    begin
      clk = 1'b1;
      while (1) #(`local_clk_period/4) clk = ~clk;
    end

  initial
    begin
      clk270 = 1'b1;
      #(`local_clk_period/8);
      #(`local_clk_period/8);
      #(`local_clk_period/8);
      while (1) #(`local_clk_period/4) clk270 = ~clk270;
    end

  initial
    begin
      clk4 = 1'b1;
      while (1) #(`local_clk_period) clk4 = ~clk4;
    end

  initial
    begin
      seed = 1;
      rst_n = 1'b0;
      tvere = 1'b0;
      tx_wr = 1'b0;
      acki = 1'b1;
      test = 0;

      // No checksum
      tx_wdata = $random(seed);
      repeat (5) @(posedge clk4);
      rst_n = 1'b1;
      repeat (2) @(posedge clk4);

      test = 10;
      write;

      repeat (17) @(posedge clk4);

      test = 20;
      write_last;
      
      repeat (20) @(posedge clk4);

      test = 30;
      write;
      write_last;

      repeat (20) @(posedge clk4);
      
      test = 40;
      // Test variable delays between successive packets
      delay = 1;
      repeat (4)
      begin
	write;
	repeat (delay)
	  @(posedge clk4);
	write_last;
	repeat (20) @(posedge clk4);
	delay = delay + 1;
	test = test + 1;
      end

      // With checksum
      test = 100;
      tvere = 1'b1;
      tx_wdata = $random(seed);
      repeat (5) @(posedge clk4);
      rst_n = 1'b1;
      repeat (2) @(posedge clk4);

      test = 110;
      write;

      repeat (17) @(posedge clk4);
      
      test = 120;
      write_last;
      
      repeat (20) @(posedge clk4);

      test = 130;
      write;
      write_last;

      repeat (20) @(posedge clk4);
      
      test = 140;
      // Test variable delays between successive packets
      delay = 1;
      repeat (4)
      begin
	write;
	repeat (delay)
	  @(posedge clk4);
	write_last;
	repeat (20) @(posedge clk4);
	delay = delay + 1;
	test = test + 1;
      end

      $finish;
    end

//---------------------------------------------------------------------------
//---------------------------------------------------------------------------
  task write;
    reg [31:0] data;
    begin
      #1 tx_wr <= 1'b1;
      expect_check <= 8'b0;
      repeat (4)
      begin
	data = $random(seed);
	tx_wdata <= {1'b0, data};
	@(posedge clk4);
	expect_check <= expect_check + data[31:24] + data[23:16] + data[15:8] + data[7:0];
      end
      #1 tx_wr <= 1'b0;
    end
  endtask

//---------------------------------------------------------------------------
//---------------------------------------------------------------------------
  task write_last;
    reg [31:0] data;
    begin
      #1 tx_wr <= 1'b1;
      expect_check <= 8'b0;
      repeat (4)
      begin
	data = $random(seed);
	tx_wdata <= {1'b1, data};
	@(posedge clk4);
	expect_check <= expect_check + data[31:24] + data[23:16] + data[15:8] + data[7:0];
      end
      #1 tx_wr <= 1'b0;
    end
  endtask

//---------------------------------------------------------------------------
//---------------------------------------------------------------------------
  lp_tx #(DEVICE) dut (.clk		(clk),
		       .clk270		(clk270),
		       .clk4		(clk4),
		       .rst_n		(rst_n),

		       .tvere		(tvere),
		       
		       .tx_wr		(tx_wr),
		       .tx_wdata	(tx_wdata),
		       .tx_wrused	(tx_wrused),
		       .tx_wrfull	(tx_wrfull),
		       
		       .clk_out		(clk_out),
		       .data_out	(data_out),
		       .acki		(acki),
		       .bcmpo_n		(bcmpo_n)
		       );

endmodule