lp_tx.do

altera fpga 和ts201的linkport接口设计

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vlib work
vmap work work

vlog C:/quartus/eda/sim_lib/altera_mf.v
vlog -reportprogress 300 -work work tx_test_harness.v
vlog -reportprogress 300 -work work ../../../source/verilog/lp_tx.v
vlog -reportprogress 300 -work work ../../../build/lp_tx/cyclone/ddr_clk.v

vsim work.tx_tb

view wave
do tx_wave.do

run -all