ddr_clk.v

来自「altera fpga 和ts201的linkport接口设计」· Verilog 代码 · 共 40 行

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module ddr_clk (datain_h,
		clk,
		dataout
		);

  input datain_h;
  input clk;
  output dataout;

  reg 	datareg;
  always @(negedge clk)
    datareg <= datain_h;

  wire 	dataout = clk ? datareg : 1'b0;
  
endmodule