lp_tx_top_cyclone.v

altera fpga 和ts201的linkport接口设计

module lp_tx_top_cyclone (clk,
			  rst_n,

			  tvere,

			  tx_wr,
			  tx_wdata,
			  tx_wrused,
			  tx_wrfull,
			  
			  clk_out,
			  data_out,
			  acki,
			  bcmpo_n
			  );

  input clk;
  input rst_n;

  input tvere;

  input tx_wr;
  input [32:0] tx_wdata;
  output [3:0] tx_wrused;
  output       tx_wrfull;
				 
  output       clk_out;
  output [3:0] data_out;
  input        acki;
  output       bcmpo_n;

  wire [3:0]   tx_wrused;
  wire 	       tx_wrfull;
  
  wire 	       clk_out;
  wire [3:0]   data_out;
  wire 	       bcmpo_n;
  
  wire 	       lp_clk;
  wire 	       lp_clk270;
  wire 	       lp_clk2;

  tx_pll tx_pll (
		 .inclk0	(clk),
		 .pllena	(1'b1),
		 .areset	(~rst_n),
		 .c0		(lp_clk),
		 .c1		(lp_clk270)
		 );

  lp_tx #("Cyclone") lp_tx (
			    .clk	(lp_clk),
			    .clk270	(lp_clk270),
			    .clk4	(clk),
			    .rst_n	(rst_n),

			    .tvere	(tvere),
			    
			    .tx_wr	(tx_wr),
			    .tx_wdata	(tx_wdata),
			    .tx_wrused	(tx_wrused),
			    .tx_wrfull	(tx_wrfull),
		       
			    .clk_out	(clk_out),
			    .data_out	(data_out),
			    .acki	(acki),
			    .bcmpo_n	(bcmpo_n)
			    );

endmodule