lp_tx_top_cyclone.map.qmsg

altera fpga 和ts201的linkport接口设计

{ "Info" "ISGN_ELABORATION_HEADER" "lp_tx:lp_tx\|dcfifo:tx_fifo " "Info (12130): Elaborated megafunction instantiation \"lp_tx:lp_tx\|dcfifo:tx_fifo\"" {  } { { "../../../source/verilog/lp_tx.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/source/verilog/lp_tx.v" 83 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lp_tx:lp_tx\|dcfifo:tx_fifo " "Info (12133): Instantiated megafunction \"lp_tx:lp_tx\|dcfifo:tx_fifo\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone " "Info (12134): Parameter \"intended_device_family\" = \"Cyclone\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 33 " "Info (12134): Parameter \"lpm_width\" = \"33\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 16 " "Info (12134): Parameter \"lpm_numwords\" = \"16\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 4 " "Info (12134): Parameter \"lpm_widthu\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clocks_are_synchronized TRUE " "Info (12134): Parameter \"clocks_are_synchronized\" = \"TRUE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type dcfifo " "Info (12134): Parameter \"lpm_type\" = \"dcfifo\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Info (12134): Parameter \"lpm_showahead\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking OFF " "Info (12134): Parameter \"overflow_checking\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking OFF " "Info (12134): Parameter \"underflow_checking\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Info (12134): Parameter \"use_eab\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register ON " "Info (12134): Parameter \"add_ram_output_register\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint RAM_BLOCK_TYPE=AUTO " "Info (12134): Parameter \"lpm_hint\" = \"RAM_BLOCK_TYPE=AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "../../../source/verilog/lp_tx.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/source/verilog/lp_tx.v" 83 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dcfifo_fbn1.tdf 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_fbn1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dcfifo_fbn1 " "Info (12023): Found entity 1: dcfifo_fbn1" {  } { { "db/dcfifo_fbn1.tdf" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/db/dcfifo_fbn1.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dcfifo_fbn1 lp_tx:lp_tx\|dcfifo:tx_fifo\|dcfifo_fbn1:auto_generated " "Info (12128): Elaborating entity \"dcfifo_fbn1\" for hierarchy \"lp_tx:lp_tx\|dcfifo:tx_fifo\|dcfifo_fbn1:auto_generated\"" {  } { { "dcfifo.tdf" "auto_generated" { Text "e:/altera/11.1/quartus/libraries/megafunctions/dcfifo.tdf" 188 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_sync_fifo_vak.tdf 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file db/alt_sync_fifo_vak.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sync_fifo_vak " "Info (12023): Found entity 1: alt_sync_fifo_vak" {  } { { "db/alt_sync_fifo_vak.tdf" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/db/alt_sync_fifo_vak.tdf" 32 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_sync_fifo_vak lp_tx:lp_tx\|dcfifo:tx_fifo\|dcfifo_fbn1:auto_generated\|alt_sync_fifo_vak:sync_fifo " "Info (12128): Elaborating entity \"alt_sync_fifo_vak\" for hierarchy \"lp_tx:lp_tx\|dcfifo:tx_fifo\|dcfifo_fbn1:auto_generated\|alt_sync_fifo_vak:sync_fifo\"" {  } { { "db/dcfifo_fbn1.tdf" "sync_fifo" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/db/dcfifo_fbn1.tdf" 40 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_q241.tdf 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file db/dpram_q241.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_q241 " "Info (12023): Found entity 1: dpram_q241" {  } { { "db/dpram_q241.tdf" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/db/dpram_q241.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpram_q241 lp_tx:lp_tx\|dcfifo:tx_fifo\|dcfifo_fbn1:auto_generated\|alt_sync_fifo_vak:sync_fifo\|dpram_q241:dpram4 " "Info (12128): Elaborating entity \"dpram_q241\" for hierarchy \"lp_tx:lp_tx\|dcfifo:tx_fifo\|dcfifo_fbn1:auto_generated\|alt_sync_fifo_vak:sync_fifo\|dpram_q241:dpram4\"" {  } { { "db/alt_sync_fifo_vak.tdf" "dpram4" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/db/alt_sync_fifo_vak.tdf" 48 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_8qh1.tdf 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_8qh1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_8qh1 " "Info (12023): Found entity 1: altsyncram_8qh1" {  } { { "db/altsyncram_8qh1.tdf" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/db/altsyncram_8qh1.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_8qh1 lp_tx:lp_tx\|dcfifo:tx_fifo\|dcfifo_fbn1:auto_generated\|alt_sync_fifo_vak:sync_fifo\|dpram_q241:dpram4\|altsyncram_8qh1:altsyncram13 " "Info (12128): Elaborating entity \"altsyncram_8qh1\" for hierarchy \"lp_tx:lp_tx\|dcfifo:tx_fifo\|dcfifo_fbn1:auto_generated\|alt_sync_fifo_vak:sync_fifo\|dpram_q241:dpram4\|altsyncram_8qh1:altsyncram13\"" {  } { { "db/dpram_q241.tdf" "altsyncram13" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/db/dpram_q241.tdf" 36 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_ne8.tdf 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_ne8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_ne8 " "Info (12023): Found entity 1: add_sub_ne8" {  } { { "db/add_sub_ne8.tdf" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/db/add_sub_ne8.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_ne8 lp_tx:lp_tx\|dcfifo:tx_fifo\|dcfifo_fbn1:auto_generated\|alt_sync_fifo_vak:sync_fifo\|add_sub_ne8:add_sub2 " "Info (12128): Elaborating entity \"add_sub_ne8\" for hierarchy \"lp_tx:lp_tx\|dcfifo:tx_fifo\|dcfifo_fbn1:auto_generated\|alt_sync_fifo_vak:sync_fifo\|add_sub_ne8:add_sub2\"" {  } { { "db/alt_sync_fifo_vak.tdf" "add_sub2" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/db/alt_sync_fifo_vak.tdf" 57 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_tv7.tdf 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_tv7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_tv7 " "Info (12023): Found entity 1: add_sub_tv7" {  } { { "db/add_sub_tv7.tdf" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/db/add_sub_tv7.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_tv7 lp_tx:lp_tx\|dcfifo:tx_fifo\|dcfifo_fbn1:auto_generated\|alt_sync_fifo_vak:sync_fifo\|add_sub_tv7:add_sub3 " "Info (12128): Elaborating entity \"add_sub_tv7\" for hierarchy \"lp_tx:lp_tx\|dcfifo:tx_fifo\|dcfifo_fbn1:auto_generated\|alt_sync_fifo_vak:sync_fifo\|add_sub_tv7:add_sub3\"" {  } { { "db/alt_sync_fifo_vak.tdf" "add_sub3" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/db/alt_sync_fifo_vak.tdf" 58 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_8ta.tdf 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_8ta.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_8ta " "Info (12023): Found entity 1: cntr_8ta" {  } { { "db/cntr_8ta.tdf" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/db/cntr_8ta.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}