lp_tx_top_cyclone.map.qmsg

altera fpga 和ts201的linkport接口设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Info: Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 11.1 Build 173 11/01/2011 SJ Full Version " "Info: Version 11.1 Build 173 11/01/2011 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 06 19:45:05 2012 " "Info: Processing started: Fri Apr 06 19:45:05 2012" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lp_tx_top_cyclone -c lp_tx_top_cyclone " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lp_tx_top_cyclone -c lp_tx_top_cyclone" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/fpga_test/ts201_altera/link_port-v1.1.0/source/verilog/lp_tx.v 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file /fpga_test/ts201_altera/link_port-v1.1.0/source/verilog/lp_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 lp_tx " "Info (12023): Found entity 1: lp_tx" {  } { { "../../../source/verilog/lp_tx.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/source/verilog/lp_tx.v" 25 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "lp_tx_top_cyclone.v 1 1 " "Warning (12125): Using design file lp_tx_top_cyclone.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lp_tx_top_cyclone " "Info (12023): Found entity 1: lp_tx_top_cyclone" {  } { { "lp_tx_top_cyclone.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/lp_tx_top_cyclone.v" 2 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "lp_tx_top_cyclone " "Info (12127): Elaborating entity \"lp_tx_top_cyclone\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "tx_pll.v 1 1 " "Warning (12125): Using design file tx_pll.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 tx_pll " "Info (12023): Found entity 1: tx_pll" {  } { { "tx_pll.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/tx_pll.v" 37 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_pll tx_pll:tx_pll " "Info (12128): Elaborating entity \"tx_pll\" for hierarchy \"tx_pll:tx_pll\"" {  } { { "lp_tx_top_cyclone.v" "tx_pll" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/lp_tx_top_cyclone.v" 50 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll tx_pll:tx_pll\|altpll:altpll_component " "Info (12128): Elaborating entity \"altpll\" for hierarchy \"tx_pll:tx_pll\|altpll:altpll_component\"" {  } { { "tx_pll.v" "altpll_component" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/tx_pll.v" 63 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "tx_pll:tx_pll\|altpll:altpll_component " "Info (12130): Elaborated megafunction instantiation \"tx_pll:tx_pll\|altpll:altpll_component\"" {  } { { "tx_pll.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/tx_pll.v" 63 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "tx_pll:tx_pll\|altpll:altpll_component " "Info (12133): Instantiated megafunction \"tx_pll:tx_pll\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 1 " "Info (12134): Parameter \"clk1_divide_by\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 2734 " "Info (12134): Parameter \"clk1_phase_shift\" = \"2734\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Info (12134): Parameter \"clk0_duty_cycle\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Info (12134): Parameter \"lpm_type\" = \"altpll\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 4 " "Info (12134): Parameter \"clk0_multiply_by\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 12500 " "Info (12134): Parameter \"inclk0_input_frequency\" = \"12500\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 1 " "Info (12134): Parameter \"clk0_divide_by\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Info (12134): Parameter \"clk1_duty_cycle\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Info (12134): Parameter \"pll_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 4 " "Info (12134): Parameter \"clk1_multiply_by\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_time_delay 0 " "Info (12134): Parameter \"clk0_time_delay\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone " "Info (12134): Parameter \"intended_device_family\" = \"Cyclone\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Info (12134): Parameter \"operation_mode\" = \"NORMAL\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Info (12134): Parameter \"compensate_clock\" = \"CLK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_time_delay 0 " "Info (12134): Parameter \"clk1_time_delay\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 391 " "Info (12134): Parameter \"clk0_phase_shift\" = \"391\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "tx_pll.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/tx_pll.v" 63 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lp_tx lp_tx:lp_tx " "Info (12128): Elaborating entity \"lp_tx\" for hierarchy \"lp_tx:lp_tx\"" {  } { { "lp_tx_top_cyclone.v" "lp_tx" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/lp_tx_top_cyclone.v" 69 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "11 7 lp_tx.v(117) " "Warning (10230): Verilog HDL assignment warning at lp_tx.v(117): truncated value with size 11 to match size of target (7)" {  } { { "../../../source/verilog/lp_tx.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/source/verilog/lp_tx.v" 117 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dcfifo lp_tx:lp_tx\|dcfifo:tx_fifo " "Info (12128): Elaborating entity \"dcfifo\" for hierarchy \"lp_tx:lp_tx\|dcfifo:tx_fifo\"" {  } { { "../../../source/verilog/lp_tx.v" "tx_fifo" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/source/verilog/lp_tx.v" 83 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}