ddio_out_qdb.tdf

altera fpga 和ts201的linkport接口设计

--altddio_out CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" WIDTH=1 aclr datain_h datain_l dataout outclock
--VERSION_BEGIN 11.1 cbx_altddio_out 2011:10:31:21:11:05:SJ cbx_cycloneii 2011:10:31:21:11:05:SJ cbx_maxii 2011:10:31:21:11:05:SJ cbx_mgl 2011:10:31:21:12:31:SJ cbx_stratix 2011:10:31:21:11:05:SJ cbx_stratixii 2011:10:31:21:11:05:SJ cbx_stratixiii 2011:10:31:21:11:05:SJ cbx_stratixv 2011:10:31:21:11:05:SJ cbx_util_mgl 2011:10:31:21:11:05:SJ  VERSION_END


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FUNCTION cyclone_io (areset, datain, inclk, inclkena, oe, outclk, outclkena, sreset)
WITH ( BUS_HOLD, INPUT_ASYNC_RESET, INPUT_POWER_UP, INPUT_REGISTER_MODE, INPUT_SYNC_RESET, OE_ASYNC_RESET, OE_POWER_UP, OE_REGISTER_MODE, OE_SYNC_RESET, OPEN_DRAIN_OUTPUT, OPERATION_MODE, OUTPUT_ASYNC_RESET, OUTPUT_POWER_UP, OUTPUT_REGISTER_MODE, OUTPUT_SYNC_RESET, TIE_OFF_OE_CLOCK_ENABLE, TIE_OFF_OUTPUT_CLOCK_ENABLE)
RETURNS ( combout, padio, regout);
FUNCTION cyclone_lcell (aclr, aload, cin, clk, dataa, datab, datac, datad, ena, inverta, regcascin, sclr, sload)
WITH ( cin0_used, cin1_used, cin_used, lut_mask, operation_mode, output_mode, power_up, register_cascade_mode, sum_lutc_input, synch_mode, x_on_violation)
RETURNS ( combout, cout, regout);

--synthesis_resources = cyclone_io 1 lut 2 
OPTIONS ALTERA_INTERNAL_OPTION = "ANALYZE_METASTABILITY=OFF;ADV_NETLIST_OPT_ALLOWED=""NEVER_ALLOW"";ALLOW_SYNCH_CTRL_USAGE=OFF;suppress_da_rule_internal=""C104,C106"";{-to output_cell_L} DDIO_OUTPUT_REGISTER=LOW;{-to output_cell_L} PRESERVE_REGISTER=ON;{-to muxa} DDIO_OUTPUT_REGISTER=HIGH";

SUBDESIGN ddio_out_qdb
( 
	aclr	:	input;
	datain_h[0..0]	:	input;
	datain_l[0..0]	:	input;
	dataout[0..0]	:	output;
	outclock	:	input;
) 
VARIABLE 
	output_cell_L[0..0] : dffe;
	ddio_outa[0..0] : cyclone_io
		WITH (
			OPERATION_MODE = "output"
		);
	muxa[0..0] : cyclone_lcell
		WITH (
			cin_used = "false",
			lut_mask = "F5A0",
			operation_mode = "normal",
			sum_lutc_input = "qfbk",
			synch_mode = "on"
		);

BEGIN 
	output_cell_L[].clk = outclock;
	output_cell_L[].clrn = (! aclr);
	output_cell_L[].d = datain_l[];
	ddio_outa[].datain = muxa[].combout;
	ddio_outa[].oe = B"1";
	muxa[].aclr = aclr;
	muxa[].clk = outclock;
	muxa[].dataa = outclock;
	muxa[].datac = datain_h[];
	muxa[].datad = output_cell_L[].q;
	muxa[].sload = B"1";
	dataout[] = ddio_outa[].padio;
END;
--VALID FILE