lp_tx_top_cyclone.hier_info

altera fpga 和ts201的linkport接口设计

clock0 => ram_block14a6.CLK0
clock0 => ram_block14a7.CLK0
clock0 => ram_block14a8.CLK0
clock0 => ram_block14a9.CLK0
clock0 => ram_block14a10.CLK0
clock0 => ram_block14a11.CLK0
clock0 => ram_block14a12.CLK0
clock0 => ram_block14a13.CLK0
clock0 => ram_block14a14.CLK0
clock0 => ram_block14a15.CLK0
clock0 => ram_block14a16.CLK0
clock0 => ram_block14a17.CLK0
clock0 => ram_block14a18.CLK0
clock0 => ram_block14a19.CLK0
clock0 => ram_block14a20.CLK0
clock0 => ram_block14a21.CLK0
clock0 => ram_block14a22.CLK0
clock0 => ram_block14a23.CLK0
clock0 => ram_block14a24.CLK0
clock0 => ram_block14a25.CLK0
clock0 => ram_block14a26.CLK0
clock0 => ram_block14a27.CLK0
clock0 => ram_block14a28.CLK0
clock0 => ram_block14a29.CLK0
clock0 => ram_block14a30.CLK0
clock0 => ram_block14a31.CLK0
clock0 => ram_block14a32.CLK0
clock1 => ram_block14a0.CLK1
clock1 => ram_block14a1.CLK1
clock1 => ram_block14a2.CLK1
clock1 => ram_block14a3.CLK1
clock1 => ram_block14a4.CLK1
clock1 => ram_block14a5.CLK1
clock1 => ram_block14a6.CLK1
clock1 => ram_block14a7.CLK1
clock1 => ram_block14a8.CLK1
clock1 => ram_block14a9.CLK1
clock1 => ram_block14a10.CLK1
clock1 => ram_block14a11.CLK1
clock1 => ram_block14a12.CLK1
clock1 => ram_block14a13.CLK1
clock1 => ram_block14a14.CLK1
clock1 => ram_block14a15.CLK1
clock1 => ram_block14a16.CLK1
clock1 => ram_block14a17.CLK1
clock1 => ram_block14a18.CLK1
clock1 => ram_block14a19.CLK1
clock1 => ram_block14a20.CLK1
clock1 => ram_block14a21.CLK1
clock1 => ram_block14a22.CLK1
clock1 => ram_block14a23.CLK1
clock1 => ram_block14a24.CLK1
clock1 => ram_block14a25.CLK1
clock1 => ram_block14a26.CLK1
clock1 => ram_block14a27.CLK1
clock1 => ram_block14a28.CLK1
clock1 => ram_block14a29.CLK1
clock1 => ram_block14a30.CLK1
clock1 => ram_block14a31.CLK1
clock1 => ram_block14a32.CLK1
clocken1 => ram_block14a0.ENA1
clocken1 => ram_block14a1.ENA1
clocken1 => ram_block14a2.ENA1
clocken1 => ram_block14a3.ENA1
clocken1 => ram_block14a4.ENA1
clocken1 => ram_block14a5.ENA1
clocken1 => ram_block14a6.ENA1
clocken1 => ram_block14a7.ENA1
clocken1 => ram_block14a8.ENA1
clocken1 => ram_block14a9.ENA1
clocken1 => ram_block14a10.ENA1
clocken1 => ram_block14a11.ENA1
clocken1 => ram_block14a12.ENA1
clocken1 => ram_block14a13.ENA1
clocken1 => ram_block14a14.ENA1
clocken1 => ram_block14a15.ENA1
clocken1 => ram_block14a16.ENA1
clocken1 => ram_block14a17.ENA1
clocken1 => ram_block14a18.ENA1
clocken1 => ram_block14a19.ENA1
clocken1 => ram_block14a20.ENA1
clocken1 => ram_block14a21.ENA1
clocken1 => ram_block14a22.ENA1
clocken1 => ram_block14a23.ENA1
clocken1 => ram_block14a24.ENA1
clocken1 => ram_block14a25.ENA1
clocken1 => ram_block14a26.ENA1
clocken1 => ram_block14a27.ENA1
clocken1 => ram_block14a28.ENA1
clocken1 => ram_block14a29.ENA1
clocken1 => ram_block14a30.ENA1
clocken1 => ram_block14a31.ENA1
clocken1 => ram_block14a32.ENA1
data_a[0] => ram_block14a0.PORTADATAIN
data_a[1] => ram_block14a1.PORTADATAIN
data_a[2] => ram_block14a2.PORTADATAIN
data_a[3] => ram_block14a3.PORTADATAIN
data_a[4] => ram_block14a4.PORTADATAIN
data_a[5] => ram_block14a5.PORTADATAIN
data_a[6] => ram_block14a6.PORTADATAIN
data_a[7] => ram_block14a7.PORTADATAIN
data_a[8] => ram_block14a8.PORTADATAIN
data_a[9] => ram_block14a9.PORTADATAIN
data_a[10] => ram_block14a10.PORTADATAIN
data_a[11] => ram_block14a11.PORTADATAIN
data_a[12] => ram_block14a12.PORTADATAIN
data_a[13] => ram_block14a13.PORTADATAIN
data_a[14] => ram_block14a14.PORTADATAIN
data_a[15] => ram_block14a15.PORTADATAIN
data_a[16] => ram_block14a16.PORTADATAIN
data_a[17] => ram_block14a17.PORTADATAIN
data_a[18] => ram_block14a18.PORTADATAIN
data_a[19] => ram_block14a19.PORTADATAIN
data_a[20] => ram_block14a20.PORTADATAIN
data_a[21] => ram_block14a21.PORTADATAIN
data_a[22] => ram_block14a22.PORTADATAIN
data_a[23] => ram_block14a23.PORTADATAIN
data_a[24] => ram_block14a24.PORTADATAIN
data_a[25] => ram_block14a25.PORTADATAIN
data_a[26] => ram_block14a26.PORTADATAIN
data_a[27] => ram_block14a27.PORTADATAIN
data_a[28] => ram_block14a28.PORTADATAIN
data_a[29] => ram_block14a29.PORTADATAIN
data_a[30] => ram_block14a30.PORTADATAIN
data_a[31] => ram_block14a31.PORTADATAIN
data_a[32] => ram_block14a32.PORTADATAIN
wren_a => ram_block14a0.PORTAWE
wren_a => ram_block14a0.ENA0
wren_a => ram_block14a1.PORTAWE
wren_a => ram_block14a1.ENA0
wren_a => ram_block14a2.PORTAWE
wren_a => ram_block14a2.ENA0
wren_a => ram_block14a3.PORTAWE
wren_a => ram_block14a3.ENA0
wren_a => ram_block14a4.PORTAWE
wren_a => ram_block14a4.ENA0
wren_a => ram_block14a5.PORTAWE
wren_a => ram_block14a5.ENA0
wren_a => ram_block14a6.PORTAWE
wren_a => ram_block14a6.ENA0
wren_a => ram_block14a7.PORTAWE
wren_a => ram_block14a7.ENA0
wren_a => ram_block14a8.PORTAWE
wren_a => ram_block14a8.ENA0
wren_a => ram_block14a9.PORTAWE
wren_a => ram_block14a9.ENA0
wren_a => ram_block14a10.PORTAWE
wren_a => ram_block14a10.ENA0
wren_a => ram_block14a11.PORTAWE
wren_a => ram_block14a11.ENA0
wren_a => ram_block14a12.PORTAWE
wren_a => ram_block14a12.ENA0
wren_a => ram_block14a13.PORTAWE
wren_a => ram_block14a13.ENA0
wren_a => ram_block14a14.PORTAWE
wren_a => ram_block14a14.ENA0
wren_a => ram_block14a15.PORTAWE
wren_a => ram_block14a15.ENA0
wren_a => ram_block14a16.PORTAWE
wren_a => ram_block14a16.ENA0
wren_a => ram_block14a17.PORTAWE
wren_a => ram_block14a17.ENA0
wren_a => ram_block14a18.PORTAWE
wren_a => ram_block14a18.ENA0
wren_a => ram_block14a19.PORTAWE
wren_a => ram_block14a19.ENA0
wren_a => ram_block14a20.PORTAWE
wren_a => ram_block14a20.ENA0
wren_a => ram_block14a21.PORTAWE
wren_a => ram_block14a21.ENA0
wren_a => ram_block14a22.PORTAWE
wren_a => ram_block14a22.ENA0
wren_a => ram_block14a23.PORTAWE
wren_a => ram_block14a23.ENA0
wren_a => ram_block14a24.PORTAWE
wren_a => ram_block14a24.ENA0
wren_a => ram_block14a25.PORTAWE
wren_a => ram_block14a25.ENA0
wren_a => ram_block14a26.PORTAWE
wren_a => ram_block14a26.ENA0
wren_a => ram_block14a27.PORTAWE
wren_a => ram_block14a27.ENA0
wren_a => ram_block14a28.PORTAWE
wren_a => ram_block14a28.ENA0
wren_a => ram_block14a29.PORTAWE
wren_a => ram_block14a29.ENA0
wren_a => ram_block14a30.PORTAWE
wren_a => ram_block14a30.ENA0
wren_a => ram_block14a31.PORTAWE
wren_a => ram_block14a31.ENA0
wren_a => ram_block14a32.PORTAWE
wren_a => ram_block14a32.ENA0


|lp_tx_top_cyclone|lp_tx:lp_tx|dcfifo:tx_fifo|dcfifo_fbn1:auto_generated|alt_sync_fifo_vak:sync_fifo|add_sub_ne8:add_sub2
dataa[0] => _.IN0
dataa[0] => _.IN0
dataa[0] => _.IN0
dataa[1] => _.IN0
dataa[1] => _.IN0
dataa[1] => _.IN0
dataa[2] => _.IN0
dataa[2] => _.IN0
dataa[2] => _.IN0
dataa[3] => _.IN0
dataa[3] => _.IN0
dataa[3] => _.IN0
datab[0] => datab_node[0].IN0
datab[1] => datab_node[1].IN0
datab[2] => datab_node[2].IN0
datab[3] => datab_node[3].IN0


|lp_tx_top_cyclone|lp_tx:lp_tx|dcfifo:tx_fifo|dcfifo_fbn1:auto_generated|alt_sync_fifo_vak:sync_fifo|add_sub_tv7:add_sub3
dataa[0] => _.IN0
dataa[0] => _.IN0
dataa[0] => _.IN0
dataa[1] => _.IN0
dataa[1] => _.IN0
dataa[1] => _.IN0
dataa[2] => _.IN0
dataa[2] => _.IN0
dataa[2] => _.IN0
dataa[3] => _.IN0
dataa[3] => _.IN0
dataa[3] => _.IN0
dataa[4] => _.IN0
dataa[4] => _.IN0
dataa[4] => _.IN0
datab[0] => datab_node[0].IN0
datab[1] => datab_node[1].IN0
datab[2] => datab_node[2].IN0
datab[3] => datab_node[3].IN0
datab[4] => datab_node[4].IN0


|lp_tx_top_cyclone|lp_tx:lp_tx|dcfifo:tx_fifo|dcfifo_fbn1:auto_generated|alt_sync_fifo_vak:sync_fifo|cntr_8ta:cntr1
aclr => counter_cella0.ACLR
aclr => counter_cella1.ACLR
aclr => counter_cella2.ACLR
aclr => counter_cella3.ACLR
aclr => counter_cella4.ACLR
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
cnt_en => counter_cella0.DATAB
cnt_en => counter_cella1.DATAB
cnt_en => counter_cella2.DATAB
cnt_en => counter_cella3.DATAB
cnt_en => counter_cella4.DATAB


|lp_tx_top_cyclone|lp_tx:lp_tx|altddio_out:lp_tx_data_3
datain_h[0] => mux[0].DATAC
datain_l[0] => output_cell_L[0].DATAIN
outclock => mux[0].CLK
outclock => mux[0].DATAA
outclock => output_cell_L[0].CLK
outclocken => mux[0].ENA
outclocken => output_cell_L[0].ENA
aclr => output_cell_L[0].IN0
aclr => mux[0].ACLR
aset => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
oe => ~NO_FANOUT~
dataout[0] <> cyclone_ddio_out:ddio_out[0].padio


|lp_tx_top_cyclone|lp_tx:lp_tx|altddio_out:lp_tx_data_3|cyclone_ddio_out:ddio_out[0]
padio <> ioatom
oe => ioatom.OE
datain => ioatom.DATAIN


|lp_tx_top_cyclone|lp_tx:lp_tx|altddio_out:lp_tx_data_2
datain_h[0] => mux[0].DATAC
datain_l[0] => output_cell_L[0].DATAIN
outclock => mux[0].CLK
outclock => mux[0].DATAA
outclock => output_cell_L[0].CLK
outclocken => mux[0].ENA
outclocken => output_cell_L[0].ENA
aclr => output_cell_L[0].IN0
aclr => mux[0].ACLR
aset => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
oe => ~NO_FANOUT~
dataout[0] <> cyclone_ddio_out:ddio_out[0].padio


|lp_tx_top_cyclone|lp_tx:lp_tx|altddio_out:lp_tx_data_2|cyclone_ddio_out:ddio_out[0]
padio <> ioatom
oe => ioatom.OE
datain => ioatom.DATAIN


|lp_tx_top_cyclone|lp_tx:lp_tx|altddio_out:lp_tx_data_1
datain_h[0] => mux[0].DATAC
datain_l[0] => output_cell_L[0].DATAIN
outclock => mux[0].CLK
outclock => mux[0].DATAA
outclock => output_cell_L[0].CLK
outclocken => mux[0].ENA
outclocken => output_cell_L[0].ENA
aclr => output_cell_L[0].IN0
aclr => mux[0].ACLR
aset => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
oe => ~NO_FANOUT~
dataout[0] <> cyclone_ddio_out:ddio_out[0].padio


|lp_tx_top_cyclone|lp_tx:lp_tx|altddio_out:lp_tx_data_1|cyclone_ddio_out:ddio_out[0]
padio <> ioatom
oe => ioatom.OE
datain => ioatom.DATAIN


|lp_tx_top_cyclone|lp_tx:lp_tx|altddio_out:lp_tx_data_0
datain_h[0] => mux[0].DATAC
datain_l[0] => output_cell_L[0].DATAIN
outclock => mux[0].CLK
outclock => mux[0].DATAA
outclock => output_cell_L[0].CLK
outclocken => mux[0].ENA
outclocken => output_cell_L[0].ENA
aclr => output_cell_L[0].IN0
aclr => mux[0].ACLR
aset => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
oe => ~NO_FANOUT~
dataout[0] <> cyclone_ddio_out:ddio_out[0].padio


|lp_tx_top_cyclone|lp_tx:lp_tx|altddio_out:lp_tx_data_0|cyclone_ddio_out:ddio_out[0]
padio <> ioatom
oe => ioatom.OE
datain => ioatom.DATAIN


|lp_tx_top_cyclone|lp_tx:lp_tx|ddr_clk:lp_tx_clk
datain_h => datareg.DATAIN
clk => comb.OUTPUTSELECT
clk => datareg.CLK