lp_tx_top_cyclone.hier_info

altera fpga 和ts201的linkport接口设计

data[30] => dpram_q241:dpram4.data[30]
data[31] => dpram_q241:dpram4.data[31]
data[32] => dpram_q241:dpram4.data[32]
rdclk => dpram_q241:dpram4.outclock
rdclk => dffe5a[4].CLK
rdclk => dffe5a[3].CLK
rdclk => dffe5a[2].CLK
rdclk => dffe5a[1].CLK
rdclk => dffe5a[0].CLK
rdclk => dffe8a[4].CLK
rdclk => dffe8a[3].CLK
rdclk => dffe8a[2].CLK
rdclk => dffe8a[1].CLK
rdclk => dffe8a[0].CLK
rdreq => dpram_q241:dpram4.outclocken
rdreq => cs6a[0].IN0
rdreq => cs6a[0].IN0
wrclk => dpram_q241:dpram4.inclock
wrclk => cntr_8ta:cntr1.clock
wrclk => dffe7a[4].CLK
wrclk => dffe7a[3].CLK
wrclk => dffe7a[2].CLK
wrclk => dffe7a[1].CLK
wrclk => dffe7a[0].CLK
wrclk => dffe9a[4].CLK
wrclk => dffe9a[3].CLK
wrclk => dffe9a[2].CLK
wrclk => dffe9a[1].CLK
wrclk => dffe9a[0].CLK
wrreq => dpram_q241:dpram4.wren
wrreq => cs10a[1].IN1
wrreq => cs10a[1].IN1
wrreq => cntr_8ta:cntr1.cnt_en


|lp_tx_top_cyclone|lp_tx:lp_tx|dcfifo:tx_fifo|dcfifo_fbn1:auto_generated|alt_sync_fifo_vak:sync_fifo|dpram_q241:dpram4
data[0] => altsyncram_8qh1:altsyncram13.data_a[0]
data[1] => altsyncram_8qh1:altsyncram13.data_a[1]
data[2] => altsyncram_8qh1:altsyncram13.data_a[2]
data[3] => altsyncram_8qh1:altsyncram13.data_a[3]
data[4] => altsyncram_8qh1:altsyncram13.data_a[4]
data[5] => altsyncram_8qh1:altsyncram13.data_a[5]
data[6] => altsyncram_8qh1:altsyncram13.data_a[6]
data[7] => altsyncram_8qh1:altsyncram13.data_a[7]
data[8] => altsyncram_8qh1:altsyncram13.data_a[8]
data[9] => altsyncram_8qh1:altsyncram13.data_a[9]
data[10] => altsyncram_8qh1:altsyncram13.data_a[10]
data[11] => altsyncram_8qh1:altsyncram13.data_a[11]
data[12] => altsyncram_8qh1:altsyncram13.data_a[12]
data[13] => altsyncram_8qh1:altsyncram13.data_a[13]
data[14] => altsyncram_8qh1:altsyncram13.data_a[14]
data[15] => altsyncram_8qh1:altsyncram13.data_a[15]
data[16] => altsyncram_8qh1:altsyncram13.data_a[16]
data[17] => altsyncram_8qh1:altsyncram13.data_a[17]
data[18] => altsyncram_8qh1:altsyncram13.data_a[18]
data[19] => altsyncram_8qh1:altsyncram13.data_a[19]
data[20] => altsyncram_8qh1:altsyncram13.data_a[20]
data[21] => altsyncram_8qh1:altsyncram13.data_a[21]
data[22] => altsyncram_8qh1:altsyncram13.data_a[22]
data[23] => altsyncram_8qh1:altsyncram13.data_a[23]
data[24] => altsyncram_8qh1:altsyncram13.data_a[24]
data[25] => altsyncram_8qh1:altsyncram13.data_a[25]
data[26] => altsyncram_8qh1:altsyncram13.data_a[26]
data[27] => altsyncram_8qh1:altsyncram13.data_a[27]
data[28] => altsyncram_8qh1:altsyncram13.data_a[28]
data[29] => altsyncram_8qh1:altsyncram13.data_a[29]
data[30] => altsyncram_8qh1:altsyncram13.data_a[30]
data[31] => altsyncram_8qh1:altsyncram13.data_a[31]
data[32] => altsyncram_8qh1:altsyncram13.data_a[32]
inclock => altsyncram_8qh1:altsyncram13.clock0
outclock => altsyncram_8qh1:altsyncram13.clock1
outclocken => altsyncram_8qh1:altsyncram13.clocken1
rdaddress[0] => altsyncram_8qh1:altsyncram13.address_b[0]
rdaddress[1] => altsyncram_8qh1:altsyncram13.address_b[1]
rdaddress[2] => altsyncram_8qh1:altsyncram13.address_b[2]
rdaddress[3] => altsyncram_8qh1:altsyncram13.address_b[3]
wraddress[0] => altsyncram_8qh1:altsyncram13.address_a[0]
wraddress[1] => altsyncram_8qh1:altsyncram13.address_a[1]
wraddress[2] => altsyncram_8qh1:altsyncram13.address_a[2]
wraddress[3] => altsyncram_8qh1:altsyncram13.address_a[3]
wren => altsyncram_8qh1:altsyncram13.wren_a


|lp_tx_top_cyclone|lp_tx:lp_tx|dcfifo:tx_fifo|dcfifo_fbn1:auto_generated|alt_sync_fifo_vak:sync_fifo|dpram_q241:dpram4|altsyncram_8qh1:altsyncram13
address_a[0] => ram_block14a0.PORTAADDR
address_a[0] => ram_block14a1.PORTAADDR
address_a[0] => ram_block14a2.PORTAADDR
address_a[0] => ram_block14a3.PORTAADDR
address_a[0] => ram_block14a4.PORTAADDR
address_a[0] => ram_block14a5.PORTAADDR
address_a[0] => ram_block14a6.PORTAADDR
address_a[0] => ram_block14a7.PORTAADDR
address_a[0] => ram_block14a8.PORTAADDR
address_a[0] => ram_block14a9.PORTAADDR
address_a[0] => ram_block14a10.PORTAADDR
address_a[0] => ram_block14a11.PORTAADDR
address_a[0] => ram_block14a12.PORTAADDR
address_a[0] => ram_block14a13.PORTAADDR
address_a[0] => ram_block14a14.PORTAADDR
address_a[0] => ram_block14a15.PORTAADDR
address_a[0] => ram_block14a16.PORTAADDR
address_a[0] => ram_block14a17.PORTAADDR
address_a[0] => ram_block14a18.PORTAADDR
address_a[0] => ram_block14a19.PORTAADDR
address_a[0] => ram_block14a20.PORTAADDR
address_a[0] => ram_block14a21.PORTAADDR
address_a[0] => ram_block14a22.PORTAADDR
address_a[0] => ram_block14a23.PORTAADDR
address_a[0] => ram_block14a24.PORTAADDR
address_a[0] => ram_block14a25.PORTAADDR
address_a[0] => ram_block14a26.PORTAADDR
address_a[0] => ram_block14a27.PORTAADDR
address_a[0] => ram_block14a28.PORTAADDR
address_a[0] => ram_block14a29.PORTAADDR
address_a[0] => ram_block14a30.PORTAADDR
address_a[0] => ram_block14a31.PORTAADDR
address_a[0] => ram_block14a32.PORTAADDR
address_a[1] => ram_block14a0.PORTAADDR1
address_a[1] => ram_block14a1.PORTAADDR1
address_a[1] => ram_block14a2.PORTAADDR1
address_a[1] => ram_block14a3.PORTAADDR1
address_a[1] => ram_block14a4.PORTAADDR1
address_a[1] => ram_block14a5.PORTAADDR1
address_a[1] => ram_block14a6.PORTAADDR1
address_a[1] => ram_block14a7.PORTAADDR1
address_a[1] => ram_block14a8.PORTAADDR1
address_a[1] => ram_block14a9.PORTAADDR1
address_a[1] => ram_block14a10.PORTAADDR1
address_a[1] => ram_block14a11.PORTAADDR1
address_a[1] => ram_block14a12.PORTAADDR1
address_a[1] => ram_block14a13.PORTAADDR1
address_a[1] => ram_block14a14.PORTAADDR1
address_a[1] => ram_block14a15.PORTAADDR1
address_a[1] => ram_block14a16.PORTAADDR1
address_a[1] => ram_block14a17.PORTAADDR1
address_a[1] => ram_block14a18.PORTAADDR1
address_a[1] => ram_block14a19.PORTAADDR1
address_a[1] => ram_block14a20.PORTAADDR1
address_a[1] => ram_block14a21.PORTAADDR1
address_a[1] => ram_block14a22.PORTAADDR1
address_a[1] => ram_block14a23.PORTAADDR1
address_a[1] => ram_block14a24.PORTAADDR1
address_a[1] => ram_block14a25.PORTAADDR1
address_a[1] => ram_block14a26.PORTAADDR1
address_a[1] => ram_block14a27.PORTAADDR1
address_a[1] => ram_block14a28.PORTAADDR1
address_a[1] => ram_block14a29.PORTAADDR1
address_a[1] => ram_block14a30.PORTAADDR1
address_a[1] => ram_block14a31.PORTAADDR1
address_a[1] => ram_block14a32.PORTAADDR1
address_a[2] => ram_block14a0.PORTAADDR2
address_a[2] => ram_block14a1.PORTAADDR2
address_a[2] => ram_block14a2.PORTAADDR2
address_a[2] => ram_block14a3.PORTAADDR2
address_a[2] => ram_block14a4.PORTAADDR2
address_a[2] => ram_block14a5.PORTAADDR2
address_a[2] => ram_block14a6.PORTAADDR2
address_a[2] => ram_block14a7.PORTAADDR2
address_a[2] => ram_block14a8.PORTAADDR2
address_a[2] => ram_block14a9.PORTAADDR2
address_a[2] => ram_block14a10.PORTAADDR2
address_a[2] => ram_block14a11.PORTAADDR2
address_a[2] => ram_block14a12.PORTAADDR2
address_a[2] => ram_block14a13.PORTAADDR2
address_a[2] => ram_block14a14.PORTAADDR2
address_a[2] => ram_block14a15.PORTAADDR2
address_a[2] => ram_block14a16.PORTAADDR2
address_a[2] => ram_block14a17.PORTAADDR2
address_a[2] => ram_block14a18.PORTAADDR2
address_a[2] => ram_block14a19.PORTAADDR2
address_a[2] => ram_block14a20.PORTAADDR2
address_a[2] => ram_block14a21.PORTAADDR2
address_a[2] => ram_block14a22.PORTAADDR2
address_a[2] => ram_block14a23.PORTAADDR2
address_a[2] => ram_block14a24.PORTAADDR2
address_a[2] => ram_block14a25.PORTAADDR2
address_a[2] => ram_block14a26.PORTAADDR2
address_a[2] => ram_block14a27.PORTAADDR2
address_a[2] => ram_block14a28.PORTAADDR2
address_a[2] => ram_block14a29.PORTAADDR2
address_a[2] => ram_block14a30.PORTAADDR2
address_a[2] => ram_block14a31.PORTAADDR2
address_a[2] => ram_block14a32.PORTAADDR2
address_a[3] => ram_block14a0.PORTAADDR3
address_a[3] => ram_block14a1.PORTAADDR3
address_a[3] => ram_block14a2.PORTAADDR3
address_a[3] => ram_block14a3.PORTAADDR3
address_a[3] => ram_block14a4.PORTAADDR3
address_a[3] => ram_block14a5.PORTAADDR3
address_a[3] => ram_block14a6.PORTAADDR3
address_a[3] => ram_block14a7.PORTAADDR3
address_a[3] => ram_block14a8.PORTAADDR3
address_a[3] => ram_block14a9.PORTAADDR3
address_a[3] => ram_block14a10.PORTAADDR3
address_a[3] => ram_block14a11.PORTAADDR3
address_a[3] => ram_block14a12.PORTAADDR3
address_a[3] => ram_block14a13.PORTAADDR3
address_a[3] => ram_block14a14.PORTAADDR3
address_a[3] => ram_block14a15.PORTAADDR3
address_a[3] => ram_block14a16.PORTAADDR3
address_a[3] => ram_block14a17.PORTAADDR3
address_a[3] => ram_block14a18.PORTAADDR3
address_a[3] => ram_block14a19.PORTAADDR3
address_a[3] => ram_block14a20.PORTAADDR3
address_a[3] => ram_block14a21.PORTAADDR3
address_a[3] => ram_block14a22.PORTAADDR3
address_a[3] => ram_block14a23.PORTAADDR3
address_a[3] => ram_block14a24.PORTAADDR3
address_a[3] => ram_block14a25.PORTAADDR3
address_a[3] => ram_block14a26.PORTAADDR3
address_a[3] => ram_block14a27.PORTAADDR3
address_a[3] => ram_block14a28.PORTAADDR3
address_a[3] => ram_block14a29.PORTAADDR3
address_a[3] => ram_block14a30.PORTAADDR3
address_a[3] => ram_block14a31.PORTAADDR3
address_a[3] => ram_block14a32.PORTAADDR3
address_b[0] => ram_block14a0.PORTBADDR
address_b[0] => ram_block14a1.PORTBADDR
address_b[0] => ram_block14a2.PORTBADDR
address_b[0] => ram_block14a3.PORTBADDR
address_b[0] => ram_block14a4.PORTBADDR
address_b[0] => ram_block14a5.PORTBADDR
address_b[0] => ram_block14a6.PORTBADDR
address_b[0] => ram_block14a7.PORTBADDR
address_b[0] => ram_block14a8.PORTBADDR
address_b[0] => ram_block14a9.PORTBADDR
address_b[0] => ram_block14a10.PORTBADDR
address_b[0] => ram_block14a11.PORTBADDR
address_b[0] => ram_block14a12.PORTBADDR
address_b[0] => ram_block14a13.PORTBADDR
address_b[0] => ram_block14a14.PORTBADDR
address_b[0] => ram_block14a15.PORTBADDR
address_b[0] => ram_block14a16.PORTBADDR
address_b[0] => ram_block14a17.PORTBADDR
address_b[0] => ram_block14a18.PORTBADDR
address_b[0] => ram_block14a19.PORTBADDR
address_b[0] => ram_block14a20.PORTBADDR
address_b[0] => ram_block14a21.PORTBADDR
address_b[0] => ram_block14a22.PORTBADDR
address_b[0] => ram_block14a23.PORTBADDR
address_b[0] => ram_block14a24.PORTBADDR
address_b[0] => ram_block14a25.PORTBADDR
address_b[0] => ram_block14a26.PORTBADDR
address_b[0] => ram_block14a27.PORTBADDR
address_b[0] => ram_block14a28.PORTBADDR
address_b[0] => ram_block14a29.PORTBADDR
address_b[0] => ram_block14a30.PORTBADDR
address_b[0] => ram_block14a31.PORTBADDR
address_b[0] => ram_block14a32.PORTBADDR
address_b[1] => ram_block14a0.PORTBADDR1
address_b[1] => ram_block14a1.PORTBADDR1
address_b[1] => ram_block14a2.PORTBADDR1
address_b[1] => ram_block14a3.PORTBADDR1
address_b[1] => ram_block14a4.PORTBADDR1
address_b[1] => ram_block14a5.PORTBADDR1
address_b[1] => ram_block14a6.PORTBADDR1
address_b[1] => ram_block14a7.PORTBADDR1
address_b[1] => ram_block14a8.PORTBADDR1
address_b[1] => ram_block14a9.PORTBADDR1
address_b[1] => ram_block14a10.PORTBADDR1
address_b[1] => ram_block14a11.PORTBADDR1
address_b[1] => ram_block14a12.PORTBADDR1
address_b[1] => ram_block14a13.PORTBADDR1
address_b[1] => ram_block14a14.PORTBADDR1
address_b[1] => ram_block14a15.PORTBADDR1
address_b[1] => ram_block14a16.PORTBADDR1
address_b[1] => ram_block14a17.PORTBADDR1
address_b[1] => ram_block14a18.PORTBADDR1
address_b[1] => ram_block14a19.PORTBADDR1
address_b[1] => ram_block14a20.PORTBADDR1
address_b[1] => ram_block14a21.PORTBADDR1
address_b[1] => ram_block14a22.PORTBADDR1
address_b[1] => ram_block14a23.PORTBADDR1
address_b[1] => ram_block14a24.PORTBADDR1
address_b[1] => ram_block14a25.PORTBADDR1
address_b[1] => ram_block14a26.PORTBADDR1
address_b[1] => ram_block14a27.PORTBADDR1
address_b[1] => ram_block14a28.PORTBADDR1
address_b[1] => ram_block14a29.PORTBADDR1
address_b[1] => ram_block14a30.PORTBADDR1
address_b[1] => ram_block14a31.PORTBADDR1
address_b[1] => ram_block14a32.PORTBADDR1
address_b[2] => ram_block14a0.PORTBADDR2
address_b[2] => ram_block14a1.PORTBADDR2
address_b[2] => ram_block14a2.PORTBADDR2
address_b[2] => ram_block14a3.PORTBADDR2
address_b[2] => ram_block14a4.PORTBADDR2
address_b[2] => ram_block14a5.PORTBADDR2
address_b[2] => ram_block14a6.PORTBADDR2
address_b[2] => ram_block14a7.PORTBADDR2
address_b[2] => ram_block14a8.PORTBADDR2
address_b[2] => ram_block14a9.PORTBADDR2
address_b[2] => ram_block14a10.PORTBADDR2
address_b[2] => ram_block14a11.PORTBADDR2
address_b[2] => ram_block14a12.PORTBADDR2
address_b[2] => ram_block14a13.PORTBADDR2
address_b[2] => ram_block14a14.PORTBADDR2
address_b[2] => ram_block14a15.PORTBADDR2
address_b[2] => ram_block14a16.PORTBADDR2
address_b[2] => ram_block14a17.PORTBADDR2
address_b[2] => ram_block14a18.PORTBADDR2
address_b[2] => ram_block14a19.PORTBADDR2
address_b[2] => ram_block14a20.PORTBADDR2
address_b[2] => ram_block14a21.PORTBADDR2
address_b[2] => ram_block14a22.PORTBADDR2
address_b[2] => ram_block14a23.PORTBADDR2
address_b[2] => ram_block14a24.PORTBADDR2
address_b[2] => ram_block14a25.PORTBADDR2
address_b[2] => ram_block14a26.PORTBADDR2
address_b[2] => ram_block14a27.PORTBADDR2
address_b[2] => ram_block14a28.PORTBADDR2
address_b[2] => ram_block14a29.PORTBADDR2
address_b[2] => ram_block14a30.PORTBADDR2
address_b[2] => ram_block14a31.PORTBADDR2
address_b[2] => ram_block14a32.PORTBADDR2
address_b[3] => ram_block14a0.PORTBADDR3
address_b[3] => ram_block14a1.PORTBADDR3
address_b[3] => ram_block14a2.PORTBADDR3
address_b[3] => ram_block14a3.PORTBADDR3
address_b[3] => ram_block14a4.PORTBADDR3
address_b[3] => ram_block14a5.PORTBADDR3
address_b[3] => ram_block14a6.PORTBADDR3
address_b[3] => ram_block14a7.PORTBADDR3
address_b[3] => ram_block14a8.PORTBADDR3
address_b[3] => ram_block14a9.PORTBADDR3
address_b[3] => ram_block14a10.PORTBADDR3
address_b[3] => ram_block14a11.PORTBADDR3
address_b[3] => ram_block14a12.PORTBADDR3
address_b[3] => ram_block14a13.PORTBADDR3
address_b[3] => ram_block14a14.PORTBADDR3
address_b[3] => ram_block14a15.PORTBADDR3
address_b[3] => ram_block14a16.PORTBADDR3
address_b[3] => ram_block14a17.PORTBADDR3
address_b[3] => ram_block14a18.PORTBADDR3
address_b[3] => ram_block14a19.PORTBADDR3
address_b[3] => ram_block14a20.PORTBADDR3
address_b[3] => ram_block14a21.PORTBADDR3
address_b[3] => ram_block14a22.PORTBADDR3
address_b[3] => ram_block14a23.PORTBADDR3
address_b[3] => ram_block14a24.PORTBADDR3
address_b[3] => ram_block14a25.PORTBADDR3
address_b[3] => ram_block14a26.PORTBADDR3
address_b[3] => ram_block14a27.PORTBADDR3
address_b[3] => ram_block14a28.PORTBADDR3
address_b[3] => ram_block14a29.PORTBADDR3
address_b[3] => ram_block14a30.PORTBADDR3
address_b[3] => ram_block14a31.PORTBADDR3
address_b[3] => ram_block14a32.PORTBADDR3
clock0 => ram_block14a0.CLK0
clock0 => ram_block14a1.CLK0
clock0 => ram_block14a2.CLK0
clock0 => ram_block14a3.CLK0
clock0 => ram_block14a4.CLK0
clock0 => ram_block14a5.CLK0