dcfifo_fbn1.tdf

altera fpga 和ts201的linkport接口设计

--dcfifo_mixed_widths ADD_RAM_OUTPUT_REGISTER="ON" CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CLOCKS_ARE_SYNCHRONIZED="TRUE" DEVICE_FAMILY="Cyclone" IGNORE_CARRY_BUFFERS="OFF" LPM_NUMWORDS=16 LPM_SHOWAHEAD="OFF" LPM_WIDTH=33 LPM_WIDTH_R=33 LPM_WIDTHU=4 LPM_WIDTHU_R=4 OVERFLOW_CHECKING="OFF" RAM_BLOCK_TYPE="AUTO" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr data q rdclk rdreq rdusedw wrclk wrfull wrreq wrusedw CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone" LOW_POWER_MODE="AUTO" lpm_hint="RAM_BLOCK_TYPE=AUTO" ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
--VERSION_BEGIN 11.1 cbx_a_gray2bin 2011:10:31:21:11:05:SJ cbx_a_graycounter 2011:10:31:21:11:05:SJ cbx_altdpram 2011:10:31:21:11:05:SJ cbx_altsyncram 2011:10:31:21:11:05:SJ cbx_cycloneii 2011:10:31:21:11:05:SJ cbx_dcfifo 2011:10:31:21:11:05:SJ cbx_fifo_common 2011:10:31:21:11:05:SJ cbx_lpm_add_sub 2011:10:31:21:11:05:SJ cbx_lpm_compare 2011:10:31:21:11:05:SJ cbx_lpm_counter 2011:10:31:21:11:05:SJ cbx_lpm_decode 2011:10:31:21:11:05:SJ cbx_lpm_mux 2011:10:31:21:11:05:SJ cbx_mgl 2011:10:31:21:12:31:SJ cbx_scfifo 2011:10:31:21:11:05:SJ cbx_stratix 2011:10:31:21:11:05:SJ cbx_stratixii 2011:10:31:21:11:05:SJ cbx_stratixiii 2011:10:31:21:11:05:SJ cbx_stratixv 2011:10:31:21:11:05:SJ cbx_util_mgl 2011:10:31:21:11:05:SJ  VERSION_END


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FUNCTION alt_sync_fifo_vak (aclr, data[32..0], rdclk, rdreq, wrclk, wrreq)
RETURNS ( q[32..0], rdempty, rdusedw[3..0], wrempty, wrfull, wrusedw[3..0]);

--synthesis_resources = lut 51 M4K 1 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF;suppress_da_rule_internal=d101";

SUBDESIGN dcfifo_fbn1
( 
	aclr	:	input;
	data[32..0]	:	input;
	q[32..0]	:	output;
	rdclk	:	input;
	rdreq	:	input;
	rdusedw[3..0]	:	output;
	wrclk	:	input;
	wrfull	:	output;
	wrreq	:	input;
	wrusedw[3..0]	:	output;
) 
VARIABLE 
	sync_fifo : alt_sync_fifo_vak;

BEGIN 
	sync_fifo.aclr = aclr;
	sync_fifo.data[] = data[];
	sync_fifo.rdclk = rdclk;
	sync_fifo.rdreq = rdreq;
	sync_fifo.wrclk = wrclk;
	sync_fifo.wrreq = wrreq;
	q[] = sync_fifo.q[];
	rdusedw[] = sync_fifo.rdusedw[];
	wrfull = sync_fifo.wrfull;
	wrusedw[] = sync_fifo.wrusedw[];
END;
--VALID FILE