lp_tx_top_cyclone.map.rpt
来自「altera fpga 和ts201的linkport接口设计」· RPT 代码 · 共 656 行 · 第 1/5 页
RPT
656 行
; |cyclone_ddio_out:ddio_out[0]| ; 0 (0) ; 0 ; 0 ; 1 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |lp_tx_top_cyclone|lp_tx:lp_tx|altddio_out:lp_tx_data_0|cyclone_ddio_out:ddio_out[0] ; ;
; |altddio_out:lp_tx_data_1| ; 2 (2) ; 2 ; 0 ; 1 ; 0 ; 0 (0) ; 1 (1) ; 1 (1) ; 0 (0) ; 1 (1) ; |lp_tx_top_cyclone|lp_tx:lp_tx|altddio_out:lp_tx_data_1 ; ;
; |cyclone_ddio_out:ddio_out[0]| ; 0 (0) ; 0 ; 0 ; 1 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |lp_tx_top_cyclone|lp_tx:lp_tx|altddio_out:lp_tx_data_1|cyclone_ddio_out:ddio_out[0] ; ;
; |altddio_out:lp_tx_data_2| ; 2 (2) ; 2 ; 0 ; 1 ; 0 ; 0 (0) ; 1 (1) ; 1 (1) ; 0 (0) ; 1 (1) ; |lp_tx_top_cyclone|lp_tx:lp_tx|altddio_out:lp_tx_data_2 ; ;
; |cyclone_ddio_out:ddio_out[0]| ; 0 (0) ; 0 ; 0 ; 1 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |lp_tx_top_cyclone|lp_tx:lp_tx|altddio_out:lp_tx_data_2|cyclone_ddio_out:ddio_out[0] ; ;
; |altddio_out:lp_tx_data_3| ; 2 (2) ; 2 ; 0 ; 1 ; 0 ; 0 (0) ; 1 (1) ; 1 (1) ; 0 (0) ; 1 (1) ; |lp_tx_top_cyclone|lp_tx:lp_tx|altddio_out:lp_tx_data_3 ; ;
; |cyclone_ddio_out:ddio_out[0]| ; 0 (0) ; 0 ; 0 ; 1 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |lp_tx_top_cyclone|lp_tx:lp_tx|altddio_out:lp_tx_data_3|cyclone_ddio_out:ddio_out[0] ; ;
; |dcfifo:tx_fifo| ; 34 (0) ; 23 ; 528 ; 0 ; 0 ; 11 (0) ; 13 (0) ; 10 (0) ; 19 (0) ; 0 (0) ; |lp_tx_top_cyclone|lp_tx:lp_tx|dcfifo:tx_fifo ; ;
; |dcfifo_fbn1:auto_generated| ; 34 (0) ; 23 ; 528 ; 0 ; 0 ; 11 (0) ; 13 (0) ; 10 (0) ; 19 (0) ; 0 (0) ; |lp_tx_top_cyclone|lp_tx:lp_tx|dcfifo:tx_fifo|dcfifo_fbn1:auto_generated ; ;
; |alt_sync_fifo_vak:sync_fifo| ; 34 (20) ; 23 ; 528 ; 0 ; 0 ; 11 (2) ; 13 (13) ; 10 (5) ; 19 (5) ; 0 (0) ; |lp_tx_top_cyclone|lp_tx:lp_tx|dcfifo:tx_fifo|dcfifo_fbn1:auto_generated|alt_sync_fifo_vak:sync_fifo ; ;
; |add_sub_ne8:add_sub2| ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 0 (0) ; 5 (5) ; 0 (0) ; |lp_tx_top_cyclone|lp_tx:lp_tx|dcfifo:tx_fifo|dcfifo_fbn1:auto_generated|alt_sync_fifo_vak:sync_fifo|add_sub_ne8:add_sub2 ; ;
; |add_sub_tv7:add_sub3| ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 0 (0) ; 4 (4) ; 0 (0) ; |lp_tx_top_cyclone|lp_tx:lp_tx|dcfifo:tx_fifo|dcfifo_fbn1:auto_generated|alt_sync_fifo_vak:sync_fifo|add_sub_tv7:add_sub3 ; ;
; |cntr_8ta:cntr1| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; 5 (5) ; 0 (0) ; |lp_tx_top_cyclone|lp_tx:lp_tx|dcfifo:tx_fifo|dcfifo_fbn1:auto_generated|alt_sync_fifo_vak:sync_fifo|cntr_8ta:cntr1 ; ;
; |dpram_q241:dpram4| ; 0 (0) ; 0 ; 528 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |lp_tx_top_cyclone|lp_tx:lp_tx|dcfifo:tx_fifo|dcfifo_fbn1:auto_generated|alt_sync_fifo_vak:sync_fifo|dpram_q241:dpram4 ; ;
; |altsyncram_8qh1:altsyncram13| ; 0 (0) ; 0 ; 528 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |lp_tx_top_cyclone|lp_tx:lp_tx|dcfifo:tx_fifo|dcfifo_fbn1:auto_generated|alt_sync_fifo_vak:sync_fifo|dpram_q241:dpram4|altsyncram_8qh1:altsyncram13 ; ;
; |ddr_clk:lp_tx_clk| ; 2 (2) ; 1 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |lp_tx_top_cyclone|lp_tx:lp_tx|ddr_clk:lp_tx_clk ; ;
; |tx_pll:tx_pll| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |lp_tx_top_cyclone|tx_pll:tx_pll ; ;
; |altpll:altpll_component| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |lp_tx_top_cyclone|tx_pll:tx_pll|altpll:altpll_component ; ;
+--------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+---------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+---------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; lp_tx:lp_tx|dcfifo:tx_fifo|dcfifo_fbn1:auto_generated|alt_sync_fifo_vak:sync_fifo|dpram_q241:dpram4|altsyncram_8qh1:altsyncram13|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 16 ; 33 ; 16 ; 33 ; 528 ; None ;
+---------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary ;
+--------+--------------+---------+--------------+--------------+----------------------------------+-------------------------------------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
+--------+--------------+---------+--------------+--------------+----------------------------------+-------------------------------------------------------------------------+
; Altera ; ALTPLL ; N/A ; N/A ; N/A ; |lp_tx_top_cyclone|tx_pll:tx_pll ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/tx_pll.v ;
+--------+--------------+---------+--------------+--------------+----------------------------------+-------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Protected by Synthesis ;
+-------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; Register Name ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ;
+-------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; lp_tx:lp_tx|altddio_out:lp_tx_data_0|output_cell_L[0] ; yes ; yes ;
; lp_tx:lp_tx|altddio_out:lp_tx_data_1|output_cell_L[0] ; yes ; yes ;
; lp_tx:lp_tx|altddio_out:lp_tx_data_2|output_cell_L[0] ; yes ; yes ;
; lp_tx:lp_tx|altddio_out:lp_tx_data_3|output_cell_L[0] ; yes ; yes ;
+-------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 131 ;
; Number of registers using Synchronous Clear ; 8 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 130 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; lp_tx:lp_tx|bcmpo_n ; 2 ;
; lp_tx:lp_tx|tx_state[0] ; 5 ;
; Total number of inverted registers = 2 ; ;
+----------------------------------------+---------+
+-----------------------------------------------------+
; Source assignments for lp_tx:lp_tx|dcfifo:tx_fifo ;
+---------------------------------+-------+------+----+
; Assignment ; Value ; From ; To ;
+---------------------------------+-------+------+----+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ;
+---------------------------------+-------+------+----+
+------------------------------------------------------------------------------+
; Source assignments for lp_tx:lp_tx|dcfifo:tx_fifo|dcfifo_fbn1:auto_generated ;
+---------------------------------+-------+------+-----------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+-------+------+-----------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ;
+---------------------------------+-------+------+-----------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for lp_tx:lp_tx|dcfifo:tx_fifo|dcfifo_fbn1:auto_generated|alt_sync_fifo_vak:sync_fifo|dpram_q241:dpram4|altsyncram_8qh1:altsyncram13 ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------+
+--------------------------------------------------------------+
; Source assignments for lp_tx:lp_tx|altddio_out:lp_tx_data_3 ;
+-------------------------+-------------+------+---------------+
; Assignment ; Value ; From ; To ;
+-------------------------+-------------+------+---------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ;
; PRESERVE_REGISTER ; ON ; - ; output_cell_L ;
; DDIO_OUTPUT_REGISTER ; LOW ; - ; output_cell_L ;
; DDIO_OUTPUT_REGISTER ; HIGH ; - ; mux ;
+-------------------------+-------------+------+---------------+
+--------------------------------------------------------------+
; Source assignments for lp_tx:lp_tx|altddio_out:lp_tx_data_2 ;
+-------------------------+-------------+------+---------------+
; Assignment ; Value ; From ; To ;
+-------------------------+-------------+------+---------------+
; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ;
; PRESERVE_REGISTER ; ON ; - ; output_cell_L ;
; DDIO_OUTPUT_REGISTER ; LOW ; - ; output_cell_L ;
; DDIO_OUTPUT_REGISTER ; HIGH ; - ; mux ;
+-------------------------+-------------+------+---------------+
+--------------------------------------------------------------+
; Source assignments for lp_tx:lp_tx|altddio_out:lp_tx_data_1 ;
+-------------------------+-------------+------+---------------+
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?