lp_tx_top_cyclone.map.rpt
来自「altera fpga 和ts201的linkport接口设计」· RPT 代码 · 共 656 行 · 第 1/5 页
RPT
656 行
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Block Design Naming ; Auto ; Auto ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
; Synthesis Seed ; 1 ; 1 ;
+----------------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 2 ;
; Maximum allowed ; 2 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
; 2 processors ; 0.0% ;
+----------------------------+-------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-----------------------------------+-----------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------------------------+-----------------------------------------------------------------------------------------+
; ../../../source/verilog/lp_tx.v ; yes ; User Verilog HDL File ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/source/verilog/lp_tx.v ;
; lp_tx_top_cyclone.v ; yes ; Auto-Found Verilog HDL File ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/lp_tx_top_cyclone.v ;
; tx_pll.v ; yes ; Auto-Found Wizard-Generated File ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/tx_pll.v ;
; altpll.tdf ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/altpll.tdf ;
; aglobal111.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/aglobal111.inc ;
; stratix_pll.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/stratix_pll.inc ;
; stratixii_pll.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/stratixii_pll.inc ;
; cycloneii_pll.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/cycloneii_pll.inc ;
; dcfifo.tdf ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/dcfifo.tdf ;
; lpm_counter.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/lpm_counter.inc ;
; lpm_add_sub.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/lpm_add_sub.inc ;
; altdpram.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/altdpram.inc ;
; a_graycounter.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/a_graycounter.inc ;
; a_fefifo.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/a_fefifo.inc ;
; a_gray2bin.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/a_gray2bin.inc ;
; dffpipe.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/dffpipe.inc ;
; alt_sync_fifo.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/alt_sync_fifo.inc ;
; lpm_compare.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/lpm_compare.inc ;
; altsyncram_fifo.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/altsyncram_fifo.inc ;
; db/dcfifo_fbn1.tdf ; yes ; Auto-Generated Megafunction ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/db/dcfifo_fbn1.tdf ;
; db/alt_sync_fifo_vak.tdf ; yes ; Auto-Generated Megafunction ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/db/alt_sync_fifo_vak.tdf ;
; db/dpram_q241.tdf ; yes ; Auto-Generated Megafunction ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/db/dpram_q241.tdf ;
; db/altsyncram_8qh1.tdf ; yes ; Auto-Generated Megafunction ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/db/altsyncram_8qh1.tdf ;
; db/add_sub_ne8.tdf ; yes ; Auto-Generated Megafunction ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/db/add_sub_ne8.tdf ;
; db/add_sub_tv7.tdf ; yes ; Auto-Generated Megafunction ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/db/add_sub_tv7.tdf ;
; db/cntr_8ta.tdf ; yes ; Auto-Generated Megafunction ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/db/cntr_8ta.tdf ;
; altddio_out.tdf ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/altddio_out.tdf ;
; stratix_ddio.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/stratix_ddio.inc ;
; cyclone_ddio.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/cyclone_ddio.inc ;
; lpm_mux.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/lpm_mux.inc ;
; stratix_lcell.inc ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/stratix_lcell.inc ;
; cyclone_ddio_out.v ; yes ; Megafunction ; e:/altera/11.1/quartus/libraries/megafunctions/cyclone_ddio_out.v ;
; ddr_clk.v ; yes ; Auto-Found Verilog HDL File ; D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/cyclone/ddr_clk.v ;
+----------------------------------+-----------------+-----------------------------------+-----------------------------------------------------------------------------------------+
+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Total logic elements ; 160 ;
; -- Combinational with no register ; 29 ;
; -- Register only ; 40 ;
; -- Combinational with a register ; 91 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 10 ;
; -- 3 input functions ; 79 ;
; -- 2 input functions ; 30 ;
; -- 1 input functions ; 1 ;
; -- 0 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 117 ;
; -- arithmetic mode ; 43 ;
; -- qfbk mode ; 4 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 12 ;
; -- asynchronous clear/load mode ; 130 ;
; ; ;
; Total registers ; 131 ;
; Total logic cells in carry chains ; 51 ;
; Virtual pins ; 39 ;
; I/O pins ; 10 ;
; Total memory bits ; 528 ;
; Total PLLs ; 1 ;
; -- PLLs ; 1 ;
; ; ;
; Maximum fan-out node ; rst_n ;
; Maximum fan-out ; 131 ;
; Total fan-out ; 1052 ;
; Average fan-out ; 4.33 ;
+---------------------------------------------+-------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+--------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+--------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |lp_tx_top_cyclone ; 160 (0) ; 131 ; 528 ; 10 ; 39 ; 29 (0) ; 40 (0) ; 91 (0) ; 51 (0) ; 4 (0) ; |lp_tx_top_cyclone ; ;
; |lp_tx:lp_tx| ; 160 (116) ; 131 ; 528 ; 4 ; 0 ; 29 (17) ; 40 (22) ; 91 (77) ; 51 (32) ; 4 (0) ; |lp_tx_top_cyclone|lp_tx:lp_tx ; ;
; |altddio_out:lp_tx_data_0| ; 2 (2) ; 2 ; 0 ; 1 ; 0 ; 0 (0) ; 1 (1) ; 1 (1) ; 0 (0) ; 1 (1) ; |lp_tx_top_cyclone|lp_tx:lp_tx|altddio_out:lp_tx_data_0 ; ;
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?