tx_pll.bsf

altera fpga 和ts201的linkport接口设计

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2003 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
*/
(header "symbol" (version "1.1"))
(symbol
	(rect 0 0 328 192)
	(text "tx_pll" (rect 164 1 205 20)(font "Arial" (font_size 10)))
	(text "inst" (rect 8 173 31 188)(font "Arial" ))
	(port
		(pt 0 72)
		(input)
		(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
		(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
		(line (pt 0 72)(pt 56 72)(line_width 1))
	)
	(port
		(pt 0 96)
		(input)
		(text "pllena" (rect 0 0 40 16)(font "Arial" (font_size 8)))
		(text "pllena" (rect 4 80 38 96)(font "Arial" (font_size 8)))
		(line (pt 0 96)(pt 56 96)(line_width 1))
	)
	(port
		(pt 0 120)
		(input)
		(text "areset" (rect 0 0 42 16)(font "Arial" (font_size 8)))
		(text "areset" (rect 4 104 40 120)(font "Arial" (font_size 8)))
		(line (pt 0 120)(pt 56 120)(line_width 1))
	)
	(port
		(pt 328 72)
		(output)
		(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
		(text "c0" (rect 311 56 325 72)(font "Arial" (font_size 8)))
		(line (pt 328 72)(pt 296 72)(line_width 1))
	)
	(port
		(pt 328 96)
		(output)
		(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
		(text "c1" (rect 311 80 325 96)(font "Arial" (font_size 8)))
		(line (pt 328 96)(pt 296 96)(line_width 1))
	)
	(drawing
		(text "inclk0 frequency: 80.000 MHz" (rect 66 67 209 81)(font "Arial" ))
		(text "Operation Mode: Normal" (rect 66 84 181 98)(font "Arial" ))
		(text "Clk " (rect 67 111 84 125)(font "Arial" ))
		(text "Ratio" (rect 93 111 117 125)(font "Arial" ))
		(text "Ph (dg)" (rect 127 111 162 125)(font "Arial" ))
		(text "Td (ns)" (rect 172 111 207 125)(font "Arial" ))
		(text "DC (%)" (rect 216 111 251 125)(font "Arial" ))
		(text "c0" (rect 71 129 83 143)(font "Arial" ))
		(text "4/1" (rect 99 129 114 143)(font "Arial" ))
		(text "45.00" (rect 132 129 159 143)(font "Arial" ))
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)