cbx_args.txt

altera fpga 和ts201的linkport接口设计

BANDWIDTH_TYPE=AUTO
CLK0_DIVIDE_BY=1
CLK0_DUTY_CYCLE=50
CLK0_MULTIPLY_BY=4
CLK0_PHASE_SHIFT=0
CLK1_DIVIDE_BY=1
CLK1_DUTY_CYCLE=50
CLK1_MULTIPLY_BY=4
CLK1_PHASE_SHIFT=1500
CLK2_DIVIDE_BY=1
CLK2_DUTY_CYCLE=50
CLK2_MULTIPLY_BY=1
CLK2_PHASE_SHIFT=0
COMPENSATE_CLOCK=CLK0
INCLK0_INPUT_FREQUENCY=8000
INTENDED_DEVICE_FAMILY=Stratix
LPM_TYPE=altpll
OPERATION_MODE=NORMAL
PLL_TYPE=AUTO
PORT_ACTIVECLOCK=PORT_UNUSED
PORT_ARESET=PORT_USED
PORT_CLKBAD0=PORT_UNUSED
PORT_CLKBAD1=PORT_UNUSED
PORT_CLKLOSS=PORT_UNUSED
PORT_CLKSWITCH=PORT_UNUSED
PORT_CONFIGUPDATE=PORT_UNUSED
PORT_FBIN=PORT_UNUSED
PORT_INCLK0=PORT_USED
PORT_INCLK1=PORT_UNUSED
PORT_LOCKED=PORT_UNUSED
PORT_PFDENA=PORT_UNUSED
PORT_PHASECOUNTERSELECT=PORT_UNUSED
PORT_PHASEDONE=PORT_UNUSED
PORT_PHASESTEP=PORT_UNUSED
PORT_PHASEUPDOWN=PORT_UNUSED
PORT_PLLENA=PORT_USED
PORT_SCANACLR=PORT_UNUSED
PORT_SCANCLK=PORT_UNUSED
PORT_SCANCLKENA=PORT_UNUSED
PORT_SCANDATA=PORT_UNUSED
PORT_SCANDATAOUT=PORT_UNUSED
PORT_SCANDONE=PORT_UNUSED
PORT_SCANREAD=PORT_UNUSED
PORT_SCANWRITE=PORT_UNUSED
PORT_clk0=PORT_USED
PORT_clk1=PORT_USED
PORT_clk2=PORT_USED
PORT_clk3=PORT_UNUSED
PORT_clk4=PORT_UNUSED
PORT_clk5=PORT_UNUSED
PORT_clkena0=PORT_UNUSED
PORT_clkena1=PORT_UNUSED
PORT_clkena2=PORT_UNUSED
PORT_clkena3=PORT_UNUSED
PORT_clkena4=PORT_UNUSED
PORT_clkena5=PORT_UNUSED
PORT_extclk0=PORT_UNUSED
PORT_extclk1=PORT_UNUSED
PORT_extclk2=PORT_UNUSED
PORT_extclk3=PORT_UNUSED
SPREAD_FREQUENCY=0
DEVICE_FAMILY=Stratix
CBX_AUTO_BLACKBOX=ALL
areset
clkena
clkena
clkena
clkena
clkena
clkena
extclkena
extclkena
extclkena
extclkena
inclk
inclk
pllena
clk
clk
clk