alt_sync_fifo_1ck.tdf

altera fpga 和ts201的linkport接口设计

--alt_sync_fifo DEVICE_FAMILY="Stratix" LPM_NUMWORDS=16 LPM_SHOWAHEAD="OFF" LPM_WIDTH=33 LPM_WIDTHU=4 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr data q rdclk rdreq rdusedw wrclk wrfull wrreq wrusedw
--VERSION_BEGIN 11.1 cbx_a_gray2bin 2011:10:31:21:11:05:SJ cbx_a_graycounter 2011:10:31:21:11:05:SJ cbx_altdpram 2011:10:31:21:11:05:SJ cbx_altsyncram 2011:10:31:21:11:05:SJ cbx_cycloneii 2011:10:31:21:11:05:SJ cbx_dcfifo 2011:10:31:21:11:05:SJ cbx_fifo_common 2011:10:31:21:11:05:SJ cbx_lpm_add_sub 2011:10:31:21:11:05:SJ cbx_lpm_compare 2011:10:31:21:11:05:SJ cbx_lpm_counter 2011:10:31:21:11:05:SJ cbx_lpm_decode 2011:10:31:21:11:05:SJ cbx_lpm_mux 2011:10:31:21:11:05:SJ cbx_mgl 2011:10:31:21:12:31:SJ cbx_scfifo 2011:10:31:21:11:05:SJ cbx_stratix 2011:10:31:21:11:05:SJ cbx_stratixii 2011:10:31:21:11:05:SJ cbx_stratixiii 2011:10:31:21:11:05:SJ cbx_stratixv 2011:10:31:21:11:05:SJ cbx_util_mgl 2011:10:31:21:11:05:SJ  VERSION_END


-- Copyright (C) 1991-2011 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION dpram_u441 (data[32..0], inclock, outclock, outclocken, rdaddress[3..0], wraddress[3..0], wren)
RETURNS ( q[32..0]);
FUNCTION carry_sum (cin, sin)
RETURNS ( cout, sout);
FUNCTION add_sub_pf8 (dataa[3..0], datab[3..0])
RETURNS ( cout, result[3..0]);
FUNCTION add_sub_v08 (dataa[4..0], datab[4..0])
RETURNS ( result[4..0]);
FUNCTION cntr_aua (aclr, clock, cnt_en)
RETURNS ( q[4..0]);

--synthesis_resources = lut 51 ram_bits (AUTO) 528 
SUBDESIGN alt_sync_fifo_1ck
( 
	aclr	:	input;
	data[32..0]	:	input;
	q[32..0]	:	output;
	rdclk	:	input;
	rdempty	:	output;
	rdreq	:	input;
	rdusedw[3..0]	:	output;
	wrclk	:	input;
	wrempty	:	output;
	wrfull	:	output;
	wrreq	:	input;
	wrusedw[3..0]	:	output;
) 
VARIABLE 
	dpram4 : dpram_u441;
	cs10a[1..0] : carry_sum;
	cs11a[4..0] : carry_sum;
	cs12a[4..0] : carry_sum;
	cs6a[4..0] : carry_sum;
	dffe5a[4..0] : dffe;
	dffe7a[4..0] : dffe;
	dffe8a[4..0] : dffe;
	dffe9a[4..0] : dffe;
	add_sub2 : add_sub_pf8;
	add_sub3 : add_sub_v08;
	cntr1 : cntr_aua;
	fast_feed_read	: WIRE;
	read_count_actual[4..0]	: WIRE;
	read_delay_stratix[4..0]	: WIRE;

BEGIN 
	dpram4.data[] = data[];
	dpram4.inclock = wrclk;
	dpram4.outclock = rdclk;
	dpram4.outclocken = rdreq;
	dpram4.rdaddress[3..0] = read_count_actual[3..0];
	dpram4.wraddress[3..0] = cntr1.q[3..0];
	dpram4.wren = wrreq;
	cs10a[].cin = ( ((! cs10a[0..0].cout) & wrreq), ((! (cntr1.q[4..4] $ dffe9a[4..4].q)) $ add_sub2.cout));
	cs10a[].sin = ( ((! cs10a[0..0].cout) & wrreq), ((! (cntr1.q[4..4] $ dffe9a[4..4].q)) $ add_sub2.cout));
	cs11a[].cin = ( ((! (cntr1.q[4..1] $ dffe9a[4..1].q)) & cs11a[3..0].cout), (! (cntr1.q[0..0] $ dffe9a[0..0].q)));
	cs11a[].sin = ( ((! (cntr1.q[4..1] $ dffe9a[4..1].q)) & cs11a[3..0].cout), (! (cntr1.q[0..0] $ dffe9a[0..0].q)));
	cs12a[].cin = ( ((! (dffe8a[4..1].q $ read_delay_stratix[4..1])) & cs12a[3..0].cout), (! (dffe8a[0..0].q $ read_delay_stratix[0..0])));
	cs12a[].sin = ( ((! (dffe8a[4..1].q $ read_delay_stratix[4..1])) & cs12a[3..0].cout), (! (dffe8a[0..0].q $ read_delay_stratix[0..0])));
	cs6a[].cin = ( (read_count_actual[4..1] & cs6a[3..0].cout), (fast_feed_read & read_count_actual[0..0]));
	cs6a[].sin = ( (read_count_actual[4..1] $ cs6a[3..0].cout), (fast_feed_read $ read_count_actual[0..0]));
	dffe5a[].clk = rdclk;
	dffe5a[].clrn = (! aclr);
	dffe5a[].d = cs6a[].sout;
	dffe7a[].clk = wrclk;
	dffe7a[].clrn = (! aclr);
	dffe7a[].d = cntr1.q[];
	dffe8a[].clk = rdclk;
	dffe8a[].clrn = (! aclr);
	dffe8a[].d = dffe7a[].q;
	dffe9a[].clk = wrclk;
	dffe9a[].clrn = (! aclr);
	dffe9a[].d = read_delay_stratix[];
	add_sub2.dataa[3..0] = cntr1.q[3..0];
	add_sub2.datab[3..0] = dffe9a[3..0].q;
	add_sub3.dataa[] = dffe8a[].q;
	add_sub3.datab[] = read_delay_stratix[];
	cntr1.aclr = aclr;
	cntr1.clock = wrclk;
	cntr1.cnt_en = wrreq;
	fast_feed_read = rdreq;
	q[] = dpram4.q[];
	rdempty = cs12a[4..4].sout;
	rdusedw[3..0] = add_sub3.result[3..0];
	read_count_actual[] = dffe5a[].q;
	read_delay_stratix[] = read_count_actual[];
	wrempty = cs11a[4..4].sout;
	wrfull = cs10a[0..0].sout;
	wrusedw[3..0] = add_sub2.result[3..0];
END;
--VALID FILE