lp_tx_stratix.hif

altera fpga 和ts201的linkport接口设计

# end
# entity
dpram_u441
# storage
db|lp_tx_stratix.(7).cnf
db|lp_tx_stratix.(7).cnf
# case_insensitive
# source_file
db|dpram_u441.tdf
bccf9222f54eec7deb7ed335a4a2643
7
# used_port {
wren
-1
3
wraddress3
-1
3
wraddress2
-1
3
wraddress1
-1
3
wraddress0
-1
3
rdaddress3
-1
3
rdaddress2
-1
3
rdaddress1
-1
3
rdaddress0
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q32
-1
3
q31
-1
3
q30
-1
3
q3
-1
3
q29
-1
3
q28
-1
3
q27
-1
3
q26
-1
3
q25
-1
3
q24
-1
3
q23
-1
3
q22
-1
3
q21
-1
3
q20
-1
3
q2
-1
3
q19
-1
3
q18
-1
3
q17
-1
3
q16
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
outclocken
-1
3
outclock
-1
3
inclock
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data32
-1
3
data31
-1
3
data30
-1
3
data3
-1
3
data29
-1
3
data28
-1
3
data27
-1
3
data26
-1
3
data25
-1
3
data24
-1
3
data23
-1
3
data22
-1
3
data21
-1
3
data20
-1
3
data2
-1
3
data19
-1
3
data18
-1
3
data17
-1
3
data16
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
lp_tx:lp_tx|dcfifo:tx_fifo|dcfifo_edn1:auto_generated|alt_sync_fifo_1ck:sync_fifo|dpram_u441:dpram4
}
# macro_sequence

# end
# entity
altsyncram_arh1
# storage
db|lp_tx_stratix.(8).cnf
db|lp_tx_stratix.(8).cnf
# case_insensitive
# source_file
db|altsyncram_arh1.tdf
76d93aeec2e021656c2b9920f7523dff
7
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
lp_tx:lp_tx|dcfifo:tx_fifo|dcfifo_edn1:auto_generated|alt_sync_fifo_1ck:sync_fifo|dpram_u441:dpram4|altsyncram_arh1:altsyncram13
}
# macro_sequence

# end
# entity
add_sub_pf8
# storage
db|lp_tx_stratix.(9).cnf
db|lp_tx_stratix.(9).cnf
# case_insensitive
# source_file
db|add_sub_pf8.tdf
5665452ed8fb12fade144679f3cdcfa
7
# used_port {
result3
-1
3
result2
-1
3
result1
-1
3
result0
-1
3
datab3
-1
3
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
cout
-1
3
}
# hierarchies {
lp_tx:lp_tx|dcfifo:tx_fifo|dcfifo_edn1:auto_generated|alt_sync_fifo_1ck:sync_fifo|add_sub_pf8:add_sub2
}
# macro_sequence

# end
# entity
add_sub_v08
# storage
db|lp_tx_stratix.(10).cnf
db|lp_tx_stratix.(10).cnf
# case_insensitive
# source_file
db|add_sub_v08.tdf
37c44f64b559b2558caf57ff5443ea
7
# used_port {
result3
-1
3
result2
-1
3
result1
-1
3
result0
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
}
# hierarchies {
lp_tx:lp_tx|dcfifo:tx_fifo|dcfifo_edn1:auto_generated|alt_sync_fifo_1ck:sync_fifo|add_sub_v08:add_sub3
}
# macro_sequence

# end
# entity
cntr_aua
# storage
db|lp_tx_stratix.(11).cnf
db|lp_tx_stratix.(11).cnf
# case_insensitive
# source_file
db|cntr_aua.tdf
2e4f1ff5daaea1aef0ab8599a138d569
7
# used_port {
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
lp_tx:lp_tx|dcfifo:tx_fifo|dcfifo_edn1:auto_generated|alt_sync_fifo_1ck:sync_fifo|cntr_aua:cntr1
}
# macro_sequence

# end
# entity
altddio_out
# storage
db|lp_tx_stratix.(12).cnf
db|lp_tx_stratix.(12).cnf
# case_insensitive
# source_file
altddio_out.tdf
96f48f3e5cbcdff4e1d987f17bc
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH
1
PARAMETER_SIGNED_DEC
USR
POWER_UP_HIGH
OFF
PARAMETER_UNKNOWN
DEF
OE_REG
UNUSED
PARAMETER_UNKNOWN
DEF
extend_oe_disable
UNUSED
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
ddio_out_seb
PARAMETER_UNKNOWN
USR
}
# used_port {
outclock
-1
3
dataout
-1
3
datain_l
-1
3
datain_h
-1
3
aclr
-1
3
}
# include_file {
aglobal111.inc
9cc1f9de5ad83fc94dd171c3f7986bd
cyclone_ddio.inc
68c2254f52b458f477f8324afea19b79
lpm_mux.inc
dd87bed9959d6126db09970164b7ba6
stratix_ddio.inc
147998ba3d6cdd6184249857c9c7e95
stratix_lcell.inc
351ee1cd010436ad5d86b5faf1fa39d
}
# hierarchies {
lp_tx:lp_tx|altddio_out:lp_tx_data_3
lp_tx:lp_tx|altddio_out:lp_tx_data_2
lp_tx:lp_tx|altddio_out:lp_tx_data_1
lp_tx:lp_tx|altddio_out:lp_tx_data_0
}
# macro_sequence

# end
# entity
stratix_ddio_out
# storage
db|lp_tx_stratix.(13).cnf
db|lp_tx_stratix.(13).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
stratix_ddio_out.v
4ff27f6583bad35f04427db3c44e96e
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
operation_mode
output
PARAMETER_STRING
DEF
ddio_mode
output
PARAMETER_STRING
DEF
output_register_mode
register
PARAMETER_STRING
DEF
output_async_reset
clear
PARAMETER_UNKNOWN
USR
output_power_up
low
PARAMETER_UNKNOWN
USR
oe_register_mode
none
PARAMETER_UNKNOWN
USR
oe_async_reset
none
PARAMETER_UNKNOWN
USR
oe_power_up
low
PARAMETER_UNKNOWN
USR
extend_oe_disable
false
PARAMETER_UNKNOWN
USR
}
# hierarchies {
lp_tx:lp_tx|altddio_out:lp_tx_data_3|stratix_ddio_out:ddio_out[0]
lp_tx:lp_tx|altddio_out:lp_tx_data_2|stratix_ddio_out:ddio_out[0]
lp_tx:lp_tx|altddio_out:lp_tx_data_1|stratix_ddio_out:ddio_out[0]
lp_tx:lp_tx|altddio_out:lp_tx_data_0|stratix_ddio_out:ddio_out[0]
}
# macro_sequence

# end
# entity
ddr_clk
# storage
db|lp_tx_stratix.(14).cnf
db|lp_tx_stratix.(14).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
ddr_clk.v
516765a929164e3368d636d28f1b754
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
lp_tx:lp_tx|ddr_clk:lp_tx_clk
}
# macro_sequence

# end
# entity
altddio_out
# storage
db|lp_tx_stratix.(15).cnf
db|lp_tx_stratix.(15).cnf
# case_insensitive
# source_file
altddio_out.tdf
96f48f3e5cbcdff4e1d987f17bc
7
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH
1
PARAMETER_SIGNED_DEC
USR
POWER_UP_HIGH
OFF
PARAMETER_UNKNOWN
DEF
OE_REG
UNUSED
PARAMETER_UNKNOWN
DEF
extend_oe_disable
UNUSED
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
ddio_out_q0b
PARAMETER_UNKNOWN
USR
}
# used_port {
outclock
-1
3
dataout
-1
3
datain_h
-1
3
datain_l
-1
1
aclr
-1
1
}
# include_file {
aglobal111.inc
9cc1f9de5ad83fc94dd171c3f7986bd
cyclone_ddio.inc
68c2254f52b458f477f8324afea19b79
lpm_mux.inc
dd87bed9959d6126db09970164b7ba6
stratix_ddio.inc
147998ba3d6cdd6184249857c9c7e95
stratix_lcell.inc
351ee1cd010436ad5d86b5faf1fa39d
}
# hierarchies {
lp_tx:lp_tx|ddr_clk:lp_tx_clk|altddio_out:lp_tx_clk
}
# macro_sequence

# end
# entity
stratix_ddio_out_no_areset
# storage
db|lp_tx_stratix.(16).cnf
db|lp_tx_stratix.(16).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
stratix_ddio_out_no_areset.v
a9b702871870c4bf5ad07124f71f9
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
areset_mode
none
PARAMETER_STRING
DEF
power_up_mode
low
PARAMETER_STRING
DEF
operation_mode
output
PARAMETER_STRING
DEF
ddio_mode
output
PARAMETER_STRING
DEF
output_register_mode
register
PARAMETER_STRING
DEF
output_async_reset
none
PARAMETER_UNKNOWN
USR
output_power_up
low
PARAMETER_UNKNOWN
USR
oe_register_mode
none
PARAMETER_UNKNOWN
USR
oe_async_reset
none
PARAMETER_UNKNOWN
USR
oe_power_up
low
PARAMETER_UNKNOWN
USR
extend_oe_disable
false
PARAMETER_UNKNOWN
USR
}
# hierarchies {
lp_tx:lp_tx|ddr_clk:lp_tx_clk|altddio_out:lp_tx_clk|stratix_ddio_out_no_areset:ddio_out[0]
}
# macro_sequence

# end
# entity
lp_tx_top_stratix
# storage
db|lp_tx_stratix.(0).cnf
db|lp_tx_stratix.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
lp_tx_top_stratix.v
a1474320fa46d05167d41c20b33224a5
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
|
}
# macro_sequence

# end
# entity
lp_tx
# storage
db|lp_tx_stratix.(3).cnf
db|lp_tx_stratix.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
|fpga_test|ts201_altera|link_port-v1.1.0|source|verilog|lp_tx.v
b9fe16248b21f1dcd65c0a4d5ff979e
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
DEVICE
Stratix
PARAMETER_STRING
USR
}
# hierarchies {
lp_tx:lp_tx
}
# macro_sequence

# end
# complete