ddio_out_seb.tdf

altera fpga 和ts201的linkport接口设计

--altddio_out CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Stratix" WIDTH=1 aclr datain_h datain_l dataout outclock
--VERSION_BEGIN 11.1 cbx_altddio_out 2011:10:31:21:11:05:SJ cbx_cycloneii 2011:10:31:21:11:05:SJ cbx_maxii 2011:10:31:21:11:05:SJ cbx_mgl 2011:10:31:21:12:31:SJ cbx_stratix 2011:10:31:21:11:05:SJ cbx_stratixii 2011:10:31:21:11:05:SJ cbx_stratixiii 2011:10:31:21:11:05:SJ cbx_stratixv 2011:10:31:21:11:05:SJ cbx_util_mgl 2011:10:31:21:11:05:SJ  VERSION_END


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FUNCTION stratix_io (areset, datain, ddiodatain, delayctrlin, inclk, inclkena, oe, outclk, outclkena, sreset)
WITH ( BUS_HOLD, DDIO_MODE, EXTEND_OE_DISABLE, INPUT_ASYNC_RESET, INPUT_POWER_UP, INPUT_REGISTER_MODE, INPUT_SYNC_RESET, OE_ASYNC_RESET, OE_POWER_UP, OE_REGISTER_MODE, OE_SYNC_RESET, OPEN_DRAIN_OUTPUT, OPERATION_MODE, OUTPUT_ASYNC_RESET, OUTPUT_POWER_UP, OUTPUT_REGISTER_MODE, OUTPUT_SYNC_RESET, SIM_DLL_PHASE_SHIFT, SIM_DQS_INPUT_FREQUENCY, TIE_OFF_OE_CLOCK_ENABLE, TIE_OFF_OUTPUT_CLOCK_ENABLE)
RETURNS ( combout, ddioregout, dqsundelayedout, padio, regout);

--synthesis_resources = stratix_io 1 
OPTIONS ALTERA_INTERNAL_OPTION = "ANALYZE_METASTABILITY=OFF";

SUBDESIGN ddio_out_seb
( 
	aclr	:	input;
	datain_h[0..0]	:	input;
	datain_l[0..0]	:	input;
	dataout[0..0]	:	output;
	outclock	:	input;
) 
VARIABLE 
	ddio_outa[0..0] : stratix_io
		WITH (
			DDIO_MODE = "output",
			OPERATION_MODE = "output",
			OUTPUT_ASYNC_RESET = "clear",
			OUTPUT_POWER_UP = "low",
			OUTPUT_REGISTER_MODE = "register",
			OUTPUT_SYNC_RESET = "none"
		);

BEGIN 
	ddio_outa[].areset = aclr;
	ddio_outa[].datain = datain_h[];
	ddio_outa[].ddiodatain = datain_l[];
	ddio_outa[].outclk = outclock;
	dataout[] = ddio_outa[].padio;
END;
--VALID FILE