📄 lp_tx_stratix.map.qmsg

📁 altera fpga 和ts201的linkport接口设计
💻 QMSG
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "stratix_ddio_out lp_tx:lp_tx\|altddio_out:lp_tx_data_3\|stratix_ddio_out:ddio_out\[0\] " "Info (12128): Elaborating entity \"stratix_ddio_out\" for hierarchy \"lp_tx:lp_tx\|altddio_out:lp_tx_data_3\|stratix_ddio_out:ddio_out\[0\]\"" {  } { { "altddio_out.tdf" "ddio_out\[0\]" { Text "e:/altera/11.1/quartus/libraries/megafunctions/altddio_out.tdf" 130 13 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lp_tx:lp_tx\|altddio_out:lp_tx_data_3\|stratix_ddio_out:ddio_out\[0\] lp_tx:lp_tx\|altddio_out:lp_tx_data_3 " "Info (12131): Elaborated megafunction instantiation \"lp_tx:lp_tx\|altddio_out:lp_tx_data_3\|stratix_ddio_out:ddio_out\[0\]\", which is child of megafunction instantiation \"lp_tx:lp_tx\|altddio_out:lp_tx_data_3\"" {  } { { "altddio_out.tdf" "" { Text "e:/altera/11.1/quartus/libraries/megafunctions/altddio_out.tdf" 130 13 0 } } { "../../../source/verilog/lp_tx.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/source/verilog/lp_tx.v" 242 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr_clk lp_tx:lp_tx\|ddr_clk:lp_tx_clk " "Info (12128): Elaborating entity \"ddr_clk\" for hierarchy \"lp_tx:lp_tx\|ddr_clk:lp_tx_clk\"" {  } { { "../../../source/verilog/lp_tx.v" "lp_tx_clk" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/source/verilog/lp_tx.v" 320 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altddio_out lp_tx:lp_tx\|ddr_clk:lp_tx_clk\|altddio_out:lp_tx_clk " "Info (12128): Elaborating entity \"altddio_out\" for hierarchy \"lp_tx:lp_tx\|ddr_clk:lp_tx_clk\|altddio_out:lp_tx_clk\"" {  } { { "ddr_clk.v" "lp_tx_clk" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/ddr_clk.v" 41 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "lp_tx:lp_tx\|ddr_clk:lp_tx_clk\|altddio_out:lp_tx_clk " "Info (12130): Elaborated megafunction instantiation \"lp_tx:lp_tx\|ddr_clk:lp_tx_clk\|altddio_out:lp_tx_clk\"" {  } { { "ddr_clk.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/ddr_clk.v" 41 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lp_tx:lp_tx\|ddr_clk:lp_tx_clk\|altddio_out:lp_tx_clk " "Info (12133): Instantiated megafunction \"lp_tx:lp_tx\|ddr_clk:lp_tx_clk\|altddio_out:lp_tx_clk\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "width 1 " "Info (12134): Parameter \"width\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Stratix " "Info (12134): Parameter \"intended_device_family\" = \"Stratix\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "oe_reg UNUSED " "Info (12134): Parameter \"oe_reg\" = \"UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "extend_oe_disable UNUSED " "Info (12134): Parameter \"extend_oe_disable\" = \"UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altddio_out " "Info (12134): Parameter \"lpm_type\" = \"altddio_out\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "ddr_clk.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/ddr_clk.v" 41 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "stratix_ddio_out_no_areset lp_tx:lp_tx\|ddr_clk:lp_tx_clk\|altddio_out:lp_tx_clk\|stratix_ddio_out_no_areset:ddio_out\[0\] " "Info (12128): Elaborating entity \"stratix_ddio_out_no_areset\" for hierarchy \"lp_tx:lp_tx\|ddr_clk:lp_tx_clk\|altddio_out:lp_tx_clk\|stratix_ddio_out_no_areset:ddio_out\[0\]\"" {  } { { "altddio_out.tdf" "ddio_out\[0\]" { Text "e:/altera/11.1/quartus/libraries/megafunctions/altddio_out.tdf" 138 13 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lp_tx:lp_tx\|ddr_clk:lp_tx_clk\|altddio_out:lp_tx_clk\|stratix_ddio_out_no_areset:ddio_out\[0\] lp_tx:lp_tx\|ddr_clk:lp_tx_clk\|altddio_out:lp_tx_clk " "Info (12131): Elaborated megafunction instantiation \"lp_tx:lp_tx\|ddr_clk:lp_tx_clk\|altddio_out:lp_tx_clk\|stratix_ddio_out_no_areset:ddio_out\[0\]\", which is child of megafunction instantiation \"lp_tx:lp_tx\|ddr_clk:lp_tx_clk\|altddio_out:lp_tx_clk\"" {  } { { "altddio_out.tdf" "" { Text "e:/altera/11.1/quartus/libraries/megafunctions/altddio_out.tdf" 138 13 0 } } { "ddr_clk.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/ddr_clk.v" 41 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "4 " "Info (13014): Ignored 4 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "4 " "Info (13019): Ignored 4 SOFT buffer(s)" {  } {  } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "" 0 -1}  } {  } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "" 0 -1}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info (18000): Registers with preset signals will power-up high" {  } { { "../../../source/verilog/lp_tx.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/source/verilog/lp_tx.v" 58 -1 0 } } { "../../../source/verilog/lp_tx.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/source/verilog/lp_tx.v" 120 -1 0 } }  } 0 18000 "Registers with preset signals will power-up high" 0 0 "" 0 -1}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Info (16010): Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "tx_pll:tx_pll\|altpll:altpll_component\|pll " "Info (16011): Adding node \"tx_pll:tx_pll\|altpll:altpll_component\|pll\"" {  } {  } 0 16011 "Adding node \"%1!s!\"" 0 0 "" 0 -1}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_NUMBER_VIRTUAL_IO" "39 " "Info (15717): Design contains 39 virtual pins; timing numbers associated with paths containing virtual pins are estimates" { { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "tx_wrused\[0\] " "Info (15719): Pin \"tx_wrused\[0\]\" is virtual output pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 25 0 0 } }  } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "tx_wrused\[1\] " "Info (15719): Pin \"tx_wrused\[1\]\" is virtual output pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 25 0 0 } }  } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "tx_wrused\[2\] " "Info (15719): Pin \"tx_wrused\[2\]\" is virtual output pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 25 0 0 } }  } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "tx_wrused\[3\] " "Info (15719): Pin \"tx_wrused\[3\]\" is virtual output pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 25 0 0 } }  } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "tx_wrfull " "Info (15719): Pin \"tx_wrfull\" is virtual output pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 26 0 0 } }  } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wr " "Info (15718): Pin \"tx_wr\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 23 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[32\] " "Info (15718): Pin \"tx_wdata\[32\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[0\] " "Info (15718): Pin \"tx_wdata\[0\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[4\] " "Info (15718): Pin \"tx_wdata\[4\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[1\] " "Info (15718): Pin \"tx_wdata\[1\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[5\] " "Info (15718): Pin \"tx_wdata\[5\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[2\] " "Info (15718): Pin \"tx_wdata\[2\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[6\] " "Info (15718): Pin \"tx_wdata\[6\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[3\] " "Info (15718): Pin \"tx_wdata\[3\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[7\] " "Info (15718): Pin \"tx_wdata\[7\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[8\] " "Info (15718): Pin \"tx_wdata\[8\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[12\] " "Info (15718): Pin \"tx_wdata\[12\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[9\] " "Info (15718): Pin \"tx_wdata\[9\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[13\] " "Info (15718): Pin \"tx_wdata\[13\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[10\] " "Info (15718): Pin \"tx_wdata\[10\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[14\] " "Info (15718): Pin \"tx_wdata\[14\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[11\] " "Info (15718): Pin \"tx_wdata\[11\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[15\] " "Info (15718): Pin \"tx_wdata\[15\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[24\] " "Info (15718): Pin \"tx_wdata\[24\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[16\] " "Info (15718): Pin \"tx_wdata\[16\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[28\] " "Info (15718): Pin \"tx_wdata\[28\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[20\] " "Info (15718): Pin \"tx_wdata\[20\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[25\] " "Info (15718): Pin \"tx_wdata\[25\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[17\] " "Info (15718): Pin \"tx_wdata\[17\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[29\] " "Info (15718): Pin \"tx_wdata\[29\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[21\] " "Info (15718): Pin \"tx_wdata\[21\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[26\] " "Info (15718): Pin \"tx_wdata\[26\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[18\] " "Info (15718): Pin \"tx_wdata\[18\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[30\] " "Info (15718): Pin \"tx_wdata\[30\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[22\] " "Info (15718): Pin \"tx_wdata\[22\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[27\] " "Info (15718): Pin \"tx_wdata\[27\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[19\] " "Info (15718): Pin \"tx_wdata\[19\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[31\] " "Info (15718): Pin \"tx_wdata\[31\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "tx_wdata\[23\] " "Info (15718): Pin \"tx_wdata\[23\]\" is virtual input pin" {  } { { "lp_tx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/lp_tx_top_stratix.v" 24 0 0 } }  } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1}  } {  } 0 15717 "Design contains %1!d! virtual pins; timing numbers associated with paths containing virtual pins are estimates" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "233 " "Info (21057): Implemented 233 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Info (21058): Implemented 4 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "6 " "Info (21059): Implemented 6 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "189 " "Info (21061): Implemented 189 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_RAMS" "33 " "Info (21064): Implemented 33 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Info (21065): Implemented 1 PLLs" {  } {  } 0 21065 "Implemented %1!d! PLLs" 0 0 "" 0 -1}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II 32-bit " "Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "468 " "Info: Peak virtual memory: 468 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 07 15:14:26 2012 " "Info: Processing ended: Sat Apr 07 15:14:26 2012" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Info: Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
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