lp_tx_stratix.hier_info

altera fpga 和ts201的linkport接口设计

|lp_tx_top_stratix
clk => clk.IN1
rst_n => rst_n.IN1
tvere => tvere.IN1
tx_wr => tx_wr.IN1
tx_wdata[0] => tx_wdata[0].IN1
tx_wdata[1] => tx_wdata[1].IN1
tx_wdata[2] => tx_wdata[2].IN1
tx_wdata[3] => tx_wdata[3].IN1
tx_wdata[4] => tx_wdata[4].IN1
tx_wdata[5] => tx_wdata[5].IN1
tx_wdata[6] => tx_wdata[6].IN1
tx_wdata[7] => tx_wdata[7].IN1
tx_wdata[8] => tx_wdata[8].IN1
tx_wdata[9] => tx_wdata[9].IN1
tx_wdata[10] => tx_wdata[10].IN1
tx_wdata[11] => tx_wdata[11].IN1
tx_wdata[12] => tx_wdata[12].IN1
tx_wdata[13] => tx_wdata[13].IN1
tx_wdata[14] => tx_wdata[14].IN1
tx_wdata[15] => tx_wdata[15].IN1
tx_wdata[16] => tx_wdata[16].IN1
tx_wdata[17] => tx_wdata[17].IN1
tx_wdata[18] => tx_wdata[18].IN1
tx_wdata[19] => tx_wdata[19].IN1
tx_wdata[20] => tx_wdata[20].IN1
tx_wdata[21] => tx_wdata[21].IN1
tx_wdata[22] => tx_wdata[22].IN1
tx_wdata[23] => tx_wdata[23].IN1
tx_wdata[24] => tx_wdata[24].IN1
tx_wdata[25] => tx_wdata[25].IN1
tx_wdata[26] => tx_wdata[26].IN1
tx_wdata[27] => tx_wdata[27].IN1
tx_wdata[28] => tx_wdata[28].IN1
tx_wdata[29] => tx_wdata[29].IN1
tx_wdata[30] => tx_wdata[30].IN1
tx_wdata[31] => tx_wdata[31].IN1
tx_wdata[32] => tx_wdata[32].IN1
acki => acki.IN1


|lp_tx_top_stratix|tx_pll:tx_pll
inclk0 => sub_wire8[0].IN1
pllena => pllena.IN1
areset => areset.IN1


|lp_tx_top_stratix|tx_pll:tx_pll|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => pll.CLK1
fbin => ~NO_FANOUT~
pllena => pll.ENABLE
clkswitch => ~NO_FANOUT~
areset => pll.ARESET
pfdena => ~NO_FANOUT~
clkena[0] => pll.ENA
clkena[1] => pll.ENA1
clkena[2] => pll.ENA2
clkena[3] => pll.ENA3
clkena[4] => pll.ENA4
clkena[5] => pll.ENA5
extclkena[0] => pll.EXTCLKENA
extclkena[1] => pll.EXTCLKENA1
extclkena[2] => pll.EXTCLKENA2
extclkena[3] => pll.EXTCLKENA3
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <> <GND>


|lp_tx_top_stratix|lp_tx:lp_tx
clk => clk.IN1
clk270 => clk270.IN4
clk4 => clk4.IN2
rst_n => _.IN1
rst_n => edges[0].ACLR
rst_n => edges[1].ACLR
rst_n => edges[2].ACLR
rst_n => edges[3].ACLR
rst_n => edges[4].ACLR
rst_n => edges[5].ACLR
rst_n => edges[6].ACLR
rst_n => edges[7].ACLR
rst_n => edges[8].ACLR
rst_n => edges[9].ACLR
rst_n => edges[10].ACLR
rst_n => edges[11].ACLR
rst_n => edges[12].ACLR
rst_n => edges[13].ACLR
rst_n => edges[14].ACLR
rst_n => edges[15].ACLR
rst_n => tx_state[0].PRESET
rst_n => tx_state[1].ACLR
rst_n => tx_state[2].ACLR
rst_n => tx_state[3].ACLR
rst_n => tx_state[4].ACLR
rst_n => tx_state[5].ACLR
rst_n => tx_state[6].ACLR
rst_n => bcmpo_n~reg0.PRESET
rst_n => acki_sync.ACLR
rst_n => acki_sync1.ACLR
rst_n => tx_rd.ACLR
rst_n => edges_dly[0].ACLR
rst_n => edges_dly[1].ACLR
rst_n => load_ddr_data_in.ACLR
rst_n => load_cksum.ACLR
rst_n => ddr_data_in[8].ACLR
rst_n => ddr_data_in[9].ACLR
rst_n => ddr_data_in[10].ACLR
rst_n => ddr_data_in[11].ACLR
rst_n => ddr_data_in[12].ACLR
rst_n => ddr_data_in[13].ACLR
rst_n => ddr_data_in[14].ACLR
rst_n => ddr_data_in[15].ACLR
rst_n => ddr_data_in[16].ACLR
rst_n => ddr_data_in[17].ACLR
rst_n => ddr_data_in[18].ACLR
rst_n => ddr_data_in[19].ACLR
rst_n => ddr_data_in[20].ACLR
rst_n => ddr_data_in[21].ACLR
rst_n => ddr_data_in[22].ACLR
rst_n => ddr_data_in[23].ACLR
rst_n => ddr_data_in[24].ACLR
rst_n => ddr_data_in[25].ACLR
rst_n => ddr_data_in[26].ACLR
rst_n => ddr_data_in[27].ACLR
rst_n => ddr_data_in[28].ACLR
rst_n => ddr_data_in[29].ACLR
rst_n => ddr_data_in[30].ACLR
rst_n => ddr_data_in[31].ACLR
rst_n => ddr_data_in[0].ACLR
rst_n => ddr_data_in[1].ACLR
rst_n => ddr_data_in[2].ACLR
rst_n => ddr_data_in[3].ACLR
rst_n => ddr_data_in[4].ACLR
rst_n => ddr_data_in[5].ACLR
rst_n => ddr_data_in[6].ACLR
rst_n => ddr_data_in[7].ACLR
rst_n => ddr_data[0].ACLR
rst_n => ddr_data[1].ACLR
rst_n => ddr_data[2].ACLR
rst_n => ddr_data[3].ACLR
rst_n => ddr_data[4].ACLR
rst_n => ddr_data[5].ACLR
rst_n => ddr_data[6].ACLR
rst_n => ddr_data[7].ACLR
rst_n => cksum_reg[0].ACLR
rst_n => cksum_reg[1].ACLR
rst_n => cksum_reg[2].ACLR
rst_n => cksum_reg[3].ACLR
rst_n => cksum_reg[4].ACLR
rst_n => cksum_reg[5].ACLR
rst_n => cksum_reg[6].ACLR
rst_n => cksum_reg[7].ACLR
rst_n => clk_en.ACLR
rst_n => clk_en_rrr.ACLR
rst_n => clk_en_rr.ACLR
rst_n => clk_en_r.ACLR
rst_n => add2_2[0].ACLR
rst_n => add2_2[1].ACLR
rst_n => add2_2[2].ACLR
rst_n => add2_2[3].ACLR
rst_n => add2_2[4].ACLR
rst_n => add2_2[5].ACLR
rst_n => add2_2[6].ACLR
rst_n => add2_2[7].ACLR
rst_n => add2_1[0].ACLR
rst_n => add2_1[1].ACLR
rst_n => add2_1[2].ACLR
rst_n => add2_1[3].ACLR
rst_n => add2_1[4].ACLR
rst_n => add2_1[5].ACLR
rst_n => add2_1[6].ACLR
rst_n => add2_1[7].ACLR
rst_n => _.IN1
rst_n => _.IN1
rst_n => _.IN1
rst_n => _.IN1
tvere => tx_state.IN1
tvere => tx_rd.IN0
tvere => tx_rd.IN0
tvere => load_cksum.IN1
tvere => clk_en_rrr.IN1
tvere => bcmpo_n.OUTPUTSELECT
tvere => tx_state.IN1
tvere => tx_rd.IN0
tvere => tx_rd.IN0
tvere => tx_rd.IN1
tx_wr => tx_wr.IN1
tx_wdata[0] => tx_wdata[0].IN1
tx_wdata[1] => tx_wdata[1].IN1
tx_wdata[2] => tx_wdata[2].IN1
tx_wdata[3] => tx_wdata[3].IN1
tx_wdata[4] => tx_wdata[4].IN1
tx_wdata[5] => tx_wdata[5].IN1
tx_wdata[6] => tx_wdata[6].IN1
tx_wdata[7] => tx_wdata[7].IN1
tx_wdata[8] => tx_wdata[8].IN1
tx_wdata[9] => tx_wdata[9].IN1
tx_wdata[10] => tx_wdata[10].IN1
tx_wdata[11] => tx_wdata[11].IN1
tx_wdata[12] => tx_wdata[12].IN1
tx_wdata[13] => tx_wdata[13].IN1
tx_wdata[14] => tx_wdata[14].IN1
tx_wdata[15] => tx_wdata[15].IN1
tx_wdata[16] => tx_wdata[16].IN1
tx_wdata[17] => tx_wdata[17].IN1
tx_wdata[18] => tx_wdata[18].IN1
tx_wdata[19] => tx_wdata[19].IN1
tx_wdata[20] => tx_wdata[20].IN1
tx_wdata[21] => tx_wdata[21].IN1
tx_wdata[22] => tx_wdata[22].IN1
tx_wdata[23] => tx_wdata[23].IN1
tx_wdata[24] => tx_wdata[24].IN1
tx_wdata[25] => tx_wdata[25].IN1
tx_wdata[26] => tx_wdata[26].IN1
tx_wdata[27] => tx_wdata[27].IN1
tx_wdata[28] => tx_wdata[28].IN1
tx_wdata[29] => tx_wdata[29].IN1
tx_wdata[30] => tx_wdata[30].IN1
tx_wdata[31] => tx_wdata[31].IN1
tx_wdata[32] => tx_wdata[32].IN1
acki => acki_sync1.DATAIN


|lp_tx_top_stratix|lp_tx:lp_tx|dcfifo:tx_fifo
data[0] => dcfifo_edn1:auto_generated.data[0]
data[1] => dcfifo_edn1:auto_generated.data[1]
data[2] => dcfifo_edn1:auto_generated.data[2]
data[3] => dcfifo_edn1:auto_generated.data[3]
data[4] => dcfifo_edn1:auto_generated.data[4]
data[5] => dcfifo_edn1:auto_generated.data[5]
data[6] => dcfifo_edn1:auto_generated.data[6]
data[7] => dcfifo_edn1:auto_generated.data[7]
data[8] => dcfifo_edn1:auto_generated.data[8]
data[9] => dcfifo_edn1:auto_generated.data[9]
data[10] => dcfifo_edn1:auto_generated.data[10]
data[11] => dcfifo_edn1:auto_generated.data[11]
data[12] => dcfifo_edn1:auto_generated.data[12]
data[13] => dcfifo_edn1:auto_generated.data[13]
data[14] => dcfifo_edn1:auto_generated.data[14]
data[15] => dcfifo_edn1:auto_generated.data[15]
data[16] => dcfifo_edn1:auto_generated.data[16]
data[17] => dcfifo_edn1:auto_generated.data[17]
data[18] => dcfifo_edn1:auto_generated.data[18]
data[19] => dcfifo_edn1:auto_generated.data[19]
data[20] => dcfifo_edn1:auto_generated.data[20]
data[21] => dcfifo_edn1:auto_generated.data[21]
data[22] => dcfifo_edn1:auto_generated.data[22]
data[23] => dcfifo_edn1:auto_generated.data[23]
data[24] => dcfifo_edn1:auto_generated.data[24]
data[25] => dcfifo_edn1:auto_generated.data[25]
data[26] => dcfifo_edn1:auto_generated.data[26]
data[27] => dcfifo_edn1:auto_generated.data[27]
data[28] => dcfifo_edn1:auto_generated.data[28]
data[29] => dcfifo_edn1:auto_generated.data[29]
data[30] => dcfifo_edn1:auto_generated.data[30]
data[31] => dcfifo_edn1:auto_generated.data[31]
data[32] => dcfifo_edn1:auto_generated.data[32]
rdclk => dcfifo_edn1:auto_generated.rdclk
rdreq => dcfifo_edn1:auto_generated.rdreq
wrclk => dcfifo_edn1:auto_generated.wrclk
wrreq => dcfifo_edn1:auto_generated.wrreq
aclr => dcfifo_edn1:auto_generated.aclr


|lp_tx_top_stratix|lp_tx:lp_tx|dcfifo:tx_fifo|dcfifo_edn1:auto_generated
aclr => alt_sync_fifo_1ck:sync_fifo.aclr
data[0] => alt_sync_fifo_1ck:sync_fifo.data[0]
data[1] => alt_sync_fifo_1ck:sync_fifo.data[1]
data[2] => alt_sync_fifo_1ck:sync_fifo.data[2]
data[3] => alt_sync_fifo_1ck:sync_fifo.data[3]
data[4] => alt_sync_fifo_1ck:sync_fifo.data[4]
data[5] => alt_sync_fifo_1ck:sync_fifo.data[5]
data[6] => alt_sync_fifo_1ck:sync_fifo.data[6]
data[7] => alt_sync_fifo_1ck:sync_fifo.data[7]
data[8] => alt_sync_fifo_1ck:sync_fifo.data[8]
data[9] => alt_sync_fifo_1ck:sync_fifo.data[9]
data[10] => alt_sync_fifo_1ck:sync_fifo.data[10]
data[11] => alt_sync_fifo_1ck:sync_fifo.data[11]
data[12] => alt_sync_fifo_1ck:sync_fifo.data[12]
data[13] => alt_sync_fifo_1ck:sync_fifo.data[13]
data[14] => alt_sync_fifo_1ck:sync_fifo.data[14]
data[15] => alt_sync_fifo_1ck:sync_fifo.data[15]
data[16] => alt_sync_fifo_1ck:sync_fifo.data[16]
data[17] => alt_sync_fifo_1ck:sync_fifo.data[17]
data[18] => alt_sync_fifo_1ck:sync_fifo.data[18]
data[19] => alt_sync_fifo_1ck:sync_fifo.data[19]
data[20] => alt_sync_fifo_1ck:sync_fifo.data[20]
data[21] => alt_sync_fifo_1ck:sync_fifo.data[21]
data[22] => alt_sync_fifo_1ck:sync_fifo.data[22]
data[23] => alt_sync_fifo_1ck:sync_fifo.data[23]
data[24] => alt_sync_fifo_1ck:sync_fifo.data[24]
data[25] => alt_sync_fifo_1ck:sync_fifo.data[25]
data[26] => alt_sync_fifo_1ck:sync_fifo.data[26]
data[27] => alt_sync_fifo_1ck:sync_fifo.data[27]
data[28] => alt_sync_fifo_1ck:sync_fifo.data[28]
data[29] => alt_sync_fifo_1ck:sync_fifo.data[29]
data[30] => alt_sync_fifo_1ck:sync_fifo.data[30]
data[31] => alt_sync_fifo_1ck:sync_fifo.data[31]
data[32] => alt_sync_fifo_1ck:sync_fifo.data[32]
rdclk => alt_sync_fifo_1ck:sync_fifo.rdclk
rdreq => alt_sync_fifo_1ck:sync_fifo.rdreq
wrclk => alt_sync_fifo_1ck:sync_fifo.wrclk
wrreq => alt_sync_fifo_1ck:sync_fifo.wrreq


|lp_tx_top_stratix|lp_tx:lp_tx|dcfifo:tx_fifo|dcfifo_edn1:auto_generated|alt_sync_fifo_1ck:sync_fifo
aclr => dffe5a[4].IN0
aclr => dffe7a[4].IN0
aclr => dffe8a[4].IN0
aclr => dffe9a[4].IN0
aclr => cntr_aua:cntr1.aclr
data[0] => dpram_u441:dpram4.data[0]
data[1] => dpram_u441:dpram4.data[1]
data[2] => dpram_u441:dpram4.data[2]
data[3] => dpram_u441:dpram4.data[3]
data[4] => dpram_u441:dpram4.data[4]
data[5] => dpram_u441:dpram4.data[5]
data[6] => dpram_u441:dpram4.data[6]
data[7] => dpram_u441:dpram4.data[7]
data[8] => dpram_u441:dpram4.data[8]
data[9] => dpram_u441:dpram4.data[9]
data[10] => dpram_u441:dpram4.data[10]
data[11] => dpram_u441:dpram4.data[11]
data[12] => dpram_u441:dpram4.data[12]
data[13] => dpram_u441:dpram4.data[13]
data[14] => dpram_u441:dpram4.data[14]
data[15] => dpram_u441:dpram4.data[15]
data[16] => dpram_u441:dpram4.data[16]
data[17] => dpram_u441:dpram4.data[17]
data[18] => dpram_u441:dpram4.data[18]
data[19] => dpram_u441:dpram4.data[19]
data[20] => dpram_u441:dpram4.data[20]
data[21] => dpram_u441:dpram4.data[21]
data[22] => dpram_u441:dpram4.data[22]
data[23] => dpram_u441:dpram4.data[23]
data[24] => dpram_u441:dpram4.data[24]
data[25] => dpram_u441:dpram4.data[25]
data[26] => dpram_u441:dpram4.data[26]
data[27] => dpram_u441:dpram4.data[27]
data[28] => dpram_u441:dpram4.data[28]
data[29] => dpram_u441:dpram4.data[29]
data[30] => dpram_u441:dpram4.data[30]
data[31] => dpram_u441:dpram4.data[31]
data[32] => dpram_u441:dpram4.data[32]
rdclk => dpram_u441:dpram4.outclock
rdclk => dffe5a[4].CLK
rdclk => dffe5a[3].CLK
rdclk => dffe5a[2].CLK