prev_cmp_lp_tx_stratix.qmsg

altera fpga 和ts201的linkport接口设计

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dcfifo_edn1 lp_tx:lp_tx\|dcfifo:tx_fifo\|dcfifo_edn1:auto_generated " "Info (12128): Elaborating entity \"dcfifo_edn1\" for hierarchy \"lp_tx:lp_tx\|dcfifo:tx_fifo\|dcfifo_edn1:auto_generated\"" {  } { { "dcfifo.tdf" "auto_generated" { Text "e:/altera/11.1/quartus/libraries/megafunctions/dcfifo.tdf" 188 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_sync_fifo_1ck.tdf 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file db/alt_sync_fifo_1ck.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sync_fifo_1ck " "Info (12023): Found entity 1: alt_sync_fifo_1ck" {  } { { "db/alt_sync_fifo_1ck.tdf" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/db/alt_sync_fifo_1ck.tdf" 32 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_sync_fifo_1ck lp_tx:lp_tx\|dcfifo:tx_fifo\|dcfifo_edn1:auto_generated\|alt_sync_fifo_1ck:sync_fifo " "Info (12128): Elaborating entity \"alt_sync_fifo_1ck\" for hierarchy \"lp_tx:lp_tx\|dcfifo:tx_fifo\|dcfifo_edn1:auto_generated\|alt_sync_fifo_1ck:sync_fifo\"" {  } { { "db/dcfifo_edn1.tdf" "sync_fifo" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/db/dcfifo_edn1.tdf" 40 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_u441.tdf 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file db/dpram_u441.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_u441 " "Info (12023): Found entity 1: dpram_u441" {  } { { "db/dpram_u441.tdf" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/db/dpram_u441.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpram_u441 lp_tx:lp_tx\|dcfifo:tx_fifo\|dcfifo_edn1:auto_generated\|alt_sync_fifo_1ck:sync_fifo\|dpram_u441:dpram4 " "Info (12128): Elaborating entity \"dpram_u441\" for hierarchy \"lp_tx:lp_tx\|dcfifo:tx_fifo\|dcfifo_edn1:auto_generated\|alt_sync_fifo_1ck:sync_fifo\|dpram_u441:dpram4\"" {  } { { "db/alt_sync_fifo_1ck.tdf" "dpram4" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/db/alt_sync_fifo_1ck.tdf" 48 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_arh1.tdf 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_arh1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_arh1 " "Info (12023): Found entity 1: altsyncram_arh1" {  } { { "db/altsyncram_arh1.tdf" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/db/altsyncram_arh1.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_arh1 lp_tx:lp_tx\|dcfifo:tx_fifo\|dcfifo_edn1:auto_generated\|alt_sync_fifo_1ck:sync_fifo\|dpram_u441:dpram4\|altsyncram_arh1:altsyncram13 " "Info (12128): Elaborating entity \"altsyncram_arh1\" for hierarchy \"lp_tx:lp_tx\|dcfifo:tx_fifo\|dcfifo_edn1:auto_generated\|alt_sync_fifo_1ck:sync_fifo\|dpram_u441:dpram4\|altsyncram_arh1:altsyncram13\"" {  } { { "db/dpram_u441.tdf" "altsyncram13" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/db/dpram_u441.tdf" 36 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_pf8.tdf 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_pf8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_pf8 " "Info (12023): Found entity 1: add_sub_pf8" {  } { { "db/add_sub_pf8.tdf" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/db/add_sub_pf8.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_pf8 lp_tx:lp_tx\|dcfifo:tx_fifo\|dcfifo_edn1:auto_generated\|alt_sync_fifo_1ck:sync_fifo\|add_sub_pf8:add_sub2 " "Info (12128): Elaborating entity \"add_sub_pf8\" for hierarchy \"lp_tx:lp_tx\|dcfifo:tx_fifo\|dcfifo_edn1:auto_generated\|alt_sync_fifo_1ck:sync_fifo\|add_sub_pf8:add_sub2\"" {  } { { "db/alt_sync_fifo_1ck.tdf" "add_sub2" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/db/alt_sync_fifo_1ck.tdf" 57 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_v08.tdf 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_v08.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_v08 " "Info (12023): Found entity 1: add_sub_v08" {  } { { "db/add_sub_v08.tdf" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/db/add_sub_v08.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_v08 lp_tx:lp_tx\|dcfifo:tx_fifo\|dcfifo_edn1:auto_generated\|alt_sync_fifo_1ck:sync_fifo\|add_sub_v08:add_sub3 " "Info (12128): Elaborating entity \"add_sub_v08\" for hierarchy \"lp_tx:lp_tx\|dcfifo:tx_fifo\|dcfifo_edn1:auto_generated\|alt_sync_fifo_1ck:sync_fifo\|add_sub_v08:add_sub3\"" {  } { { "db/alt_sync_fifo_1ck.tdf" "add_sub3" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/db/alt_sync_fifo_1ck.tdf" 58 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_aua.tdf 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_aua.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_aua " "Info (12023): Found entity 1: cntr_aua" {  } { { "db/cntr_aua.tdf" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/db/cntr_aua.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_aua lp_tx:lp_tx\|dcfifo:tx_fifo\|dcfifo_edn1:auto_generated\|alt_sync_fifo_1ck:sync_fifo\|cntr_aua:cntr1 " "Info (12128): Elaborating entity \"cntr_aua\" for hierarchy \"lp_tx:lp_tx\|dcfifo:tx_fifo\|dcfifo_edn1:auto_generated\|alt_sync_fifo_1ck:sync_fifo\|cntr_aua:cntr1\"" {  } { { "db/alt_sync_fifo_1ck.tdf" "cntr1" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_tx/stratix/db/alt_sync_fifo_1ck.tdf" 59 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altddio_out lp_tx:lp_tx\|altddio_out:lp_tx_data_3 " "Info (12128): Elaborating entity \"altddio_out\" for hierarchy \"lp_tx:lp_tx\|altddio_out:lp_tx_data_3\"" {  } { { "../../../source/verilog/lp_tx.v" "lp_tx_data_3" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/source/verilog/lp_tx.v" 242 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "lp_tx:lp_tx\|altddio_out:lp_tx_data_3 " "Info (12130): Elaborated megafunction instantiation \"lp_tx:lp_tx\|altddio_out:lp_tx_data_3\"" {  } { { "../../../source/verilog/lp_tx.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/source/verilog/lp_tx.v" 242 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lp_tx:lp_tx\|altddio_out:lp_tx_data_3 " "Info (12133): Instantiated megafunction \"lp_tx:lp_tx\|altddio_out:lp_tx_data_3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "width 1 " "Info (12134): Parameter \"width\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Stratix " "Info (12134): Parameter \"intended_device_family\" = \"Stratix\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "oe_reg UNUSED " "Info (12134): Parameter \"oe_reg\" = \"UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "extend_oe_disable UNUSED " "Info (12134): Parameter \"extend_oe_disable\" = \"UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altddio_out " "Info (12134): Parameter \"lpm_type\" = \"altddio_out\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "../../../source/verilog/lp_tx.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/source/verilog/lp_tx.v" 242 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "stratix_ddio_out lp_tx:lp_tx\|altddio_out:lp_tx_data_3\|stratix_ddio_out:ddio_out\[0\] " "Info (12128): Elaborating entity \"stratix_ddio_out\" for hierarchy \"lp_tx:lp_tx\|altddio_out:lp_tx_data_3\|stratix_ddio_out:ddio_out\[0\]\"" {  } { { "altddio_out.tdf" "ddio_out\[0\]" { Text "e:/altera/11.1/quartus/libraries/megafunctions/altddio_out.tdf" 130 13 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}