lp_tx_stratix.qsf

altera fpga 和ts201的linkport接口设计

# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 11.1 Build 173 11/01/2011 SJ Full Version
# Date created = 19:23:57  April 06, 2012
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		lp_tx_stratix_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY Stratix
set_global_assignment -name DEVICE EP1S10F484C5
set_global_assignment -name TOP_LEVEL_ENTITY lp_tx_top_stratix
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 11.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:23:57  APRIL 06, 2012"
set_global_assignment -name LAST_QUARTUS_VERSION 11.1
set_instance_assignment -name CUT ON -from tx_wdata -to * -entity lp_tx_top_stratix
set_instance_assignment -name MULTICYCLE 4 -from "lp_tx:lp_tx|dcfifo:tx_fifo*" -to "lp_tx:lp_tx|ddr_data_in*" -entity lp_tx_top_stratix
set_instance_assignment -name MULTICYCLE 2 -from "lp_tx:lp_tx|cksum_reg" -to "lp_tx:lp_tx|ddr_data" -entity lp_tx_top_stratix
set_instance_assignment -name VIRTUAL_PIN ON -to tx_wdata -entity lp_tx_top_stratix
set_instance_assignment -name VIRTUAL_PIN ON -to tx_wr -entity lp_tx_top_stratix
set_instance_assignment -name VIRTUAL_PIN ON -to tx_wrfull -entity lp_tx_top_stratix
set_instance_assignment -name VIRTUAL_PIN ON -to tx_wrused -entity lp_tx_top_stratix
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name VERILOG_FILE tx_pll.v
set_global_assignment -name VERILOG_FILE lp_tx_top_stratix.v
set_global_assignment -name VERILOG_FILE ddr_clk.v
set_global_assignment -name VERILOG_FILE ../../../source/verilog/lp_tx.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top