ddr_clk.v

altera fpga 和ts201的linkport接口设计

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module ddr_clk (datain_h,
		clk,
		dataout
		);

  input datain_h;
  input clk;
  output dataout;

  // Stratix version uses altddio_out
  altddio_out lp_tx_clk (
			 .datain_h	(datain_h),
			 .datain_l	(1'b0),
			 .outclock	(clk),
			 .aclr		(1'b0),
			 .dataout	(dataout)
			 );
  defparam  
	    lp_tx_clk.width = 1,
	    lp_tx_clk.intended_device_family = "Stratix",
	    lp_tx_clk.oe_reg = "UNUSED",
	    lp_tx_clk.extend_oe_disable = "UNUSED",
	    lp_tx_clk.lpm_type = "altddio_out";
  
endmodule