lp_tx_stratix.flow.rpt

altera fpga 和ts201的linkport接口设计

Flow report for lp_tx_stratix
Sat Apr 07 15:14:26 2012
Quartus II 32-bit Version 11.1 Build 173 11/01/2011 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Non-Default Global Settings
  5. Flow Elapsed Time
  6. Flow OS Summary
  7. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2011 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------+
; Flow Summary                                                          ;
+---------------------------+-------------------------------------------+
; Flow Status               ; Successful - Sat Apr 07 15:14:26 2012     ;
; Quartus II 32-bit Version ; 11.1 Build 173 11/01/2011 SJ Full Version ;
; Revision Name             ; lp_tx_stratix                             ;
; Top-level Entity Name     ; lp_tx_top_stratix                         ;
; Family                    ; Stratix                                   ;
; Device                    ; EP1S10F484C5                              ;
; Timing Models             ; Final                                     ;
; Total logic elements      ; 150                                       ;
; Total pins                ; 10                                        ;
; Total virtual pins        ; 39                                        ;
; Total memory bits         ; 528                                       ;
; DSP block 9-bit elements  ; 0                                         ;
; Total PLLs                ; 1                                         ;
; Total DLLs                ; 0                                         ;
+---------------------------+-------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 04/07/2012 15:14:23 ;
; Main task         ; Compilation         ;
; Revision Name     ; lp_tx_stratix       ;
+-------------------+---------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings                                                                                    ;
+-------------------------------------+------------------------------+---------------+-------------------+------------+
; Assignment Name                     ; Value                        ; Default Value ; Entity Name       ; Section Id ;
+-------------------------------------+------------------------------+---------------+-------------------+------------+
; COMPILER_SIGNATURE_ID               ; 165400990265.133378286205692 ; --            ; --                ; --         ;
; PARTITION_COLOR                     ; 16764057                     ; --            ; lp_tx_top_stratix ; Top        ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING        ; --            ; lp_tx_top_stratix ; Top        ;
; PARTITION_NETLIST_TYPE              ; SOURCE                       ; --            ; lp_tx_top_stratix ; Top        ;
; TOP_LEVEL_ENTITY                    ; lp_tx_top_stratix            ; lp_tx_stratix ; --                ; --         ;
+-------------------------------------+------------------------------+---------------+-------------------+------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time                                                                                                        ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:05     ; 1.0                     ; 468 MB              ; 00:00:04                           ;
; Total                ; 00:00:05     ; --                      ; --                  ; 00:00:04                           ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+


+-----------------------------------------------------------------------------------+
; Flow OS Summary                                                                   ;
+----------------------+------------------+-----------+------------+----------------+
; Module Name          ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
+----------------------+------------------+-----------+------------+----------------+
; Analysis & Synthesis ; zgl-PC           ; Windows 7 ; 6.1        ; i686           ;
+----------------------+------------------+-----------+------------+----------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off lp_tx_stratix -c lp_tx_stratix