lp_rx_top_cyclone.map.qmsg

altera fpga 和ts201的linkport接口设计

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_fefifo_qec lp_rx:lp_rx\|dcfifo:rx_fifo\|dcfifo_1nm1:auto_generated\|a_fefifo_qec:read_state " "Info (12128): Elaborating entity \"a_fefifo_qec\" for hierarchy \"lp_rx:lp_rx\|dcfifo:rx_fifo\|dcfifo_1nm1:auto_generated\|a_fefifo_qec:read_state\"" {  } { { "db/dcfifo_1nm1.tdf" "read_state" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/cyclone/db/dcfifo_1nm1.tdf" 56 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_3bc.tdf 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file db/a_fefifo_3bc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_3bc " "Info (12023): Found entity 1: a_fefifo_3bc" {  } { { "db/a_fefifo_3bc.tdf" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/cyclone/db/a_fefifo_3bc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_fefifo_3bc lp_rx:lp_rx\|dcfifo:rx_fifo\|dcfifo_1nm1:auto_generated\|a_fefifo_3bc:write_state " "Info (12128): Elaborating entity \"a_fefifo_3bc\" for hierarchy \"lp_rx:lp_rx\|dcfifo:rx_fifo\|dcfifo_1nm1:auto_generated\|a_fefifo_3bc:write_state\"" {  } { { "db/dcfifo_1nm1.tdf" "write_state" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/cyclone/db/dcfifo_1nm1.tdf" 57 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_gray2bin_o4b.tdf 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file db/a_gray2bin_o4b.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_gray2bin_o4b " "Info (12023): Found entity 1: a_gray2bin_o4b" {  } { { "db/a_gray2bin_o4b.tdf" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/cyclone/db/a_gray2bin_o4b.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_gray2bin_o4b lp_rx:lp_rx\|dcfifo:rx_fifo\|dcfifo_1nm1:auto_generated\|a_gray2bin_o4b:gray2bin_rs_nbwp " "Info (12128): Elaborating entity \"a_gray2bin_o4b\" for hierarchy \"lp_rx:lp_rx\|dcfifo:rx_fifo\|dcfifo_1nm1:auto_generated\|a_gray2bin_o4b:gray2bin_rs_nbwp\"" {  } { { "db/dcfifo_1nm1.tdf" "gray2bin_rs_nbwp" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/cyclone/db/dcfifo_1nm1.tdf" 58 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_graycounter_s06.tdf 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_s06.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_graycounter_s06 " "Info (12023): Found entity 1: a_graycounter_s06" {  } { { "db/a_graycounter_s06.tdf" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/cyclone/db/a_graycounter_s06.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_graycounter_s06 lp_rx:lp_rx\|dcfifo:rx_fifo\|dcfifo_1nm1:auto_generated\|a_graycounter_s06:rdptr_g " "Info (12128): Elaborating entity \"a_graycounter_s06\" for hierarchy \"lp_rx:lp_rx\|dcfifo:rx_fifo\|dcfifo_1nm1:auto_generated\|a_graycounter_s06:rdptr_g\"" {  } { { "db/dcfifo_1nm1.tdf" "rdptr_g" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/cyclone/db/dcfifo_1nm1.tdf" 60 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_t241.tdf 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file db/dpram_t241.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_t241 " "Info (12023): Found entity 1: dpram_t241" {  } { { "db/dpram_t241.tdf" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/cyclone/db/dpram_t241.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpram_t241 lp_rx:lp_rx\|dcfifo:rx_fifo\|dcfifo_1nm1:auto_generated\|dpram_t241:fiforam " "Info (12128): Elaborating entity \"dpram_t241\" for hierarchy \"lp_rx:lp_rx\|dcfifo:rx_fifo\|dcfifo_1nm1:auto_generated\|dpram_t241:fiforam\"" {  } { { "db/dcfifo_1nm1.tdf" "fiforam" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/cyclone/db/dcfifo_1nm1.tdf" 62 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_eqh1.tdf 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_eqh1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_eqh1 " "Info (12023): Found entity 1: altsyncram_eqh1" {  } { { "db/altsyncram_eqh1.tdf" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/cyclone/db/altsyncram_eqh1.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_eqh1 lp_rx:lp_rx\|dcfifo:rx_fifo\|dcfifo_1nm1:auto_generated\|dpram_t241:fiforam\|altsyncram_eqh1:altsyncram6 " "Info (12128): Elaborating entity \"altsyncram_eqh1\" for hierarchy \"lp_rx:lp_rx\|dcfifo:rx_fifo\|dcfifo_1nm1:auto_generated\|dpram_t241:fiforam\|altsyncram_eqh1:altsyncram6\"" {  } { { "db/dpram_t241.tdf" "altsyncram6" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/cyclone/db/dpram_t241.tdf" 36 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_ed9.tdf 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_ed9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_ed9 " "Info (12023): Found entity 1: dffpipe_ed9" {  } { { "db/dffpipe_ed9.tdf" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/cyclone/db/dffpipe_ed9.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_ed9 lp_rx:lp_rx\|dcfifo:rx_fifo\|dcfifo_1nm1:auto_generated\|dffpipe_ed9:dffpipe_rdbuw " "Info (12128): Elaborating entity \"dffpipe_ed9\" for hierarchy \"lp_rx:lp_rx\|dcfifo:rx_fifo\|dcfifo_1nm1:auto_generated\|dffpipe_ed9:dffpipe_rdbuw\"" {  } { { "db/dcfifo_1nm1.tdf" "dffpipe_rdbuw" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/cyclone/db/dcfifo_1nm1.tdf" 64 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_synch_pipe_mc8.tdf 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_mc8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_synch_pipe_mc8 " "Info (12023): Found entity 1: alt_synch_pipe_mc8" {  } { { "db/alt_synch_pipe_mc8.tdf" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/cyclone/db/alt_synch_pipe_mc8.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_synch_pipe_mc8 lp_rx:lp_rx\|dcfifo:rx_fifo\|dcfifo_1nm1:auto_generated\|alt_synch_pipe_mc8:dffpipe_rs_dgwp " "Info (12128): Elaborating entity \"alt_synch_pipe_mc8\" for hierarchy \"lp_rx:lp_rx\|dcfifo:rx_fifo\|dcfifo_1nm1:auto_generated\|alt_synch_pipe_mc8:dffpipe_rs_dgwp\"" {  } { { "db/dcfifo_1nm1.tdf" "dffpipe_rs_dgwp" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/cyclone/db/dcfifo_1nm1.tdf" 67 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}