a_fefifo_qec.tdf

altera fpga 和ts201的linkport接口设计

--a_fefifo LPM_NUMWORDS=128 lpm_widthad=7 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USEDW_IN_DELAY=1 aclr clock empty rreq usedw_in
--VERSION_BEGIN 11.1 cbx_cycloneii 2011:10:31:21:11:05:SJ cbx_fifo_common 2011:10:31:21:11:05:SJ cbx_lpm_add_sub 2011:10:31:21:11:05:SJ cbx_lpm_compare 2011:10:31:21:11:05:SJ cbx_lpm_counter 2011:10:31:21:11:05:SJ cbx_lpm_decode 2011:10:31:21:11:05:SJ cbx_mgl 2011:10:31:21:12:31:SJ cbx_stratix 2011:10:31:21:11:05:SJ cbx_stratixii 2011:10:31:21:11:05:SJ  VERSION_END


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--synthesis_resources = lut 16 
SUBDESIGN a_fefifo_qec
( 
	aclr	:	input;
	clock	:	input;
	empty	:	output;
	rreq	:	input;
	usedw_in[6..0]	:	input;
) 
VARIABLE 
	b_full : dffe;
	b_non_empty : dffe;
	b_one : dffe;
	llreq : dffe;
	cmp_full_aeb_int	:	WIRE;
	cmp_full_agb_int	:	WIRE;
	cmp_full_ageb	:	WIRE;
	cmp_full_dataa[6..0]	:	WIRE;
	cmp_full_datab[6..0]	:	WIRE;
	equal_one[6..0]	: WIRE;
	equal_two[6..0]	: WIRE;
	equal_zero[6..0]	: WIRE;
	is_one0	: WIRE;
	is_one1	: WIRE;
	is_one2	: WIRE;
	is_one3	: WIRE;
	is_one4	: WIRE;
	is_one5	: WIRE;
	is_one6	: WIRE;
	is_two0	: WIRE;
	is_two1	: WIRE;
	is_two2	: WIRE;
	is_two3	: WIRE;
	is_two4	: WIRE;
	is_two5	: WIRE;
	is_two6	: WIRE;
	is_zero0	: WIRE;
	is_zero1	: WIRE;
	is_zero2	: WIRE;
	is_zero3	: WIRE;
	is_zero4	: WIRE;
	is_zero5	: WIRE;
	is_zero6	: WIRE;
	usedw[6..0]	: WIRE;

BEGIN 
	b_full.clk = clock;
	b_full.clrn = (! aclr);
	b_full.d = cmp_full_ageb;
	b_non_empty.clk = clock;
	b_non_empty.clrn = (! aclr);
	b_non_empty.d = (((b_non_empty.q & (b_non_empty.q $ (((is_one6 & (! llreq.q)) # (is_two6 & llreq.q)) & rreq))) # ((b_one.q & (! is_zero6)) & (! is_one6))) # (((! b_one.q) & (! b_non_empty.q)) & (! is_zero6)));
	b_one.clk = clock;
	b_one.clrn = (! aclr);
	b_one.d = ((! b_one.q) & (b_non_empty.q & (((is_one6 & (! llreq.q)) # (is_two6 & llreq.q)) & rreq)));
	llreq.clk = clock;
	llreq.clrn = (! aclr);
	llreq.d = (rreq & b_non_empty.q);
	IF (cmp_full_dataa[] == cmp_full_datab[]) THEN
		cmp_full_aeb_int = VCC;
	ELSE
		cmp_full_aeb_int = GND;
	END IF;
	IF (cmp_full_dataa[] > cmp_full_datab[]) THEN
		cmp_full_agb_int = VCC;
	ELSE
		cmp_full_agb_int = GND;
	END IF;
	cmp_full_ageb = cmp_full_agb_int # cmp_full_aeb_int;
	cmp_full_dataa[] = usedw[];
	cmp_full_datab[] = B"1111101";
	empty = (! b_non_empty.q);
	equal_one[] = ( B"1", B"1", B"1", B"1", B"1", B"1", B"0");
	equal_two[] = ( B"1", B"1", B"1", B"1", B"1", B"0", B"1");
	equal_zero[] = ( B"1", B"1", B"1", B"1", B"1", B"1", B"1");
	is_one0 = (usedw[0..0] $ equal_one[0..0]);
	is_one1 = ((usedw[1..1] $ equal_one[1..1]) & is_one0);
	is_one2 = ((usedw[2..2] $ equal_one[2..2]) & is_one1);
	is_one3 = ((usedw[3..3] $ equal_one[3..3]) & is_one2);
	is_one4 = ((usedw[4..4] $ equal_one[4..4]) & is_one3);
	is_one5 = ((usedw[5..5] $ equal_one[5..5]) & is_one4);
	is_one6 = ((usedw[6..6] $ equal_one[6..6]) & is_one5);
	is_two0 = (usedw[0..0] $ equal_two[0..0]);
	is_two1 = ((usedw[1..1] $ equal_two[1..1]) & is_two0);
	is_two2 = ((usedw[2..2] $ equal_two[2..2]) & is_two1);
	is_two3 = ((usedw[3..3] $ equal_two[3..3]) & is_two2);
	is_two4 = ((usedw[4..4] $ equal_two[4..4]) & is_two3);
	is_two5 = ((usedw[5..5] $ equal_two[5..5]) & is_two4);
	is_two6 = ((usedw[6..6] $ equal_two[6..6]) & is_two5);
	is_zero0 = (usedw[0..0] $ equal_zero[0..0]);
	is_zero1 = ((usedw[1..1] $ equal_zero[1..1]) & is_zero0);
	is_zero2 = ((usedw[2..2] $ equal_zero[2..2]) & is_zero1);
	is_zero3 = ((usedw[3..3] $ equal_zero[3..3]) & is_zero2);
	is_zero4 = ((usedw[4..4] $ equal_zero[4..4]) & is_zero3);
	is_zero5 = ((usedw[5..5] $ equal_zero[5..5]) & is_zero4);
	is_zero6 = ((usedw[6..6] $ equal_zero[6..6]) & is_zero5);
	usedw[] = usedw_in[];
END;
--VALID FILE