cntr_ata.tdf

altera fpga 和ts201的linkport接口设计

--lpm_counter DEVICE_FAMILY="Cyclone" lpm_direction="UP" lpm_port_updown="PORT_UNUSED" lpm_width=7 aclr clock cnt_en q
--VERSION_BEGIN 11.1 cbx_cycloneii 2011:10:31:21:11:05:SJ cbx_lpm_add_sub 2011:10:31:21:11:05:SJ cbx_lpm_compare 2011:10:31:21:11:05:SJ cbx_lpm_counter 2011:10:31:21:11:05:SJ cbx_lpm_decode 2011:10:31:21:11:05:SJ cbx_mgl 2011:10:31:21:12:31:SJ cbx_stratix 2011:10:31:21:11:05:SJ cbx_stratixii 2011:10:31:21:11:05:SJ  VERSION_END


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FUNCTION cyclone_lcell (aclr, aload, cin, clk, dataa, datab, datac, datad, ena, inverta, regcascin, sclr, sload)
WITH ( cin0_used, cin1_used, cin_used, lut_mask, operation_mode, output_mode, power_up, register_cascade_mode, sum_lutc_input, synch_mode, x_on_violation)
RETURNS ( combout, cout, regout);

--synthesis_resources = lut 7 
SUBDESIGN cntr_ata
( 
	aclr	:	input;
	clock	:	input;
	cnt_en	:	input;
	q[6..0]	:	output;
) 
VARIABLE 
	counter_cella0 : cyclone_lcell
		WITH (
			cin_used = "false",
			lut_mask = "66AA",
			operation_mode = "arithmetic",
			synch_mode = "on"
		);
	counter_cella1 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "6AA0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella2 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "6AA0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella3 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "6AA0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella4 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "6AA0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella5 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "6AA0",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella6 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "6AA0",
			operation_mode = "normal",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	aclr_actual	: WIRE;
	clk_en	: NODE;
	data[6..0]	: NODE;
	s_val[6..0]	: WIRE;
	safe_q[6..0]	: WIRE;
	sclr	: NODE;
	sload	: NODE;
	sset	: NODE;
	sset_node	: WIRE;

BEGIN 
	counter_cella[6..0].aclr = aclr_actual;
	counter_cella[6..0].aload = B"0000000";
	counter_cella[1].cin = counter_cella[0].cout;
	counter_cella[2].cin = counter_cella[1].cout;
	counter_cella[3].cin = counter_cella[2].cout;
	counter_cella[4].cin = counter_cella[3].cout;
	counter_cella[5].cin = counter_cella[4].cout;
	counter_cella[6].cin = counter_cella[5].cout;
	counter_cella[6..0].clk = clock;
	counter_cella[6..0].dataa = safe_q[];
	counter_cella[6..0].datab = cnt_en;
	counter_cella[6..0].datac = ((sset & s_val[]) # ((! sset) & data[]));
	counter_cella[6].datad = B"1";
	counter_cella[6..0].ena = clk_en;
	counter_cella[6..0].sclr = sclr;
	counter_cella[6..0].sload = (sset_node # sload);
	aclr_actual = aclr;
	clk_en = VCC;
	data[] = GND;
	q[] = safe_q[];
	s_val[] = B"1111111";
	safe_q[] = counter_cella[6..0].regout;
	sclr = GND;
	sload = GND;
	sset = GND;
	sset_node = B"0";
END;
--VALID FILE