lp_rx_top_cyclone.esf

altera fpga 和ts201的linkport接口设计

TIMING_REQUIREMENTS
{
	inclock : CLOCK_SETTINGS = inclock;
	datain : TH_REQUIREMENT = 0.6ns;
	datain : TSU_REQUIREMENT = 0.6ns;
	rvere -> * : CUT = ON;
}
OPTIONS_FOR_INDIVIDUAL_NODES_ONLY
{
	datain : FAST_INPUT_REGISTER = OFF;
	rdata : VIRTUAL_PIN = ON;
	empty : VIRTUAL_PIN = ON;
	rdreq : VIRTUAL_PIN = ON;
	rcser : VIRTUAL_PIN = ON;
	rvere : VIRTUAL_PIN = ON;
}