dffpipe_gd9.tdf

altera fpga 和ts201的linkport接口设计

--dffpipe DELAY=3 WIDTH=7 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
--VERSION_BEGIN 11.1 cbx_mgl 2011:10:31:21:12:31:SJ cbx_stratixii 2011:10:31:21:11:05:SJ cbx_util_mgl 2011:10:31:21:11:05:SJ  VERSION_END


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--synthesis_resources = lut 21 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";

SUBDESIGN dffpipe_gd9
( 
	clock	:	input;
	clrn	:	input;
	d[6..0]	:	input;
	q[6..0]	:	output;
) 
VARIABLE 
	dffe10a[6..0] : dffe;
	dffe11a[6..0] : dffe;
	dffe12a[6..0] : dffe;
	ena	: NODE;
	prn	: NODE;
	sclr	: NODE;

BEGIN 
	dffe10a[].clk = clock;
	dffe10a[].clrn = clrn;
	dffe10a[].d = (d[] & (! sclr));
	dffe10a[].ena = ena;
	dffe10a[].prn = prn;
	dffe11a[].clk = clock;
	dffe11a[].clrn = clrn;
	dffe11a[].d = (dffe10a[].q & (! sclr));
	dffe11a[].ena = ena;
	dffe11a[].prn = prn;
	dffe12a[].clk = clock;
	dffe12a[].clrn = clrn;
	dffe12a[].d = (dffe11a[].q & (! sclr));
	dffe12a[].ena = ena;
	dffe12a[].prn = prn;
	ena = VCC;
	prn = VCC;
	q[] = dffe12a[].q;
	sclr = GND;
END;
--VALID FILE