dpram_1541.tdf

altera fpga 和ts201的linkport接口设计

--altdpram DEVICE_FAMILY="Stratix" INTENDED_DEVICE_FAMILY="Stratix" lpm_hint="RAM_BLOCK_TYPE=AUTO" OUTDATA_REG="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR="OFF" RDCONTROL_REG="UNREGISTERED" SUPPRESS_MEMORY_CONVERSION_WARNINGS="ON" USE_EAB="ON" WIDTH=33 WIDTHAD=7 data inclock outclock outclocken q rdaddress wraddress wren CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO"
--VERSION_BEGIN 11.1 cbx_altdpram 2011:10:31:21:11:05:SJ cbx_altsyncram 2011:10:31:21:11:05:SJ cbx_cycloneii 2011:10:31:21:11:05:SJ cbx_lpm_add_sub 2011:10:31:21:11:05:SJ cbx_lpm_compare 2011:10:31:21:11:05:SJ cbx_lpm_decode 2011:10:31:21:11:05:SJ cbx_lpm_mux 2011:10:31:21:11:05:SJ cbx_mgl 2011:10:31:21:12:31:SJ cbx_stratix 2011:10:31:21:11:05:SJ cbx_stratixii 2011:10:31:21:11:05:SJ cbx_stratixiii 2011:10:31:21:11:05:SJ cbx_stratixv 2011:10:31:21:11:05:SJ cbx_util_mgl 2011:10:31:21:11:05:SJ  VERSION_END


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FUNCTION altsyncram_grh1 (address_a[6..0], address_b[6..0], clock0, clock1, clocken1, data_a[32..0], wren_a)
RETURNS ( q_b[32..0]);

--synthesis_resources = ram_bits (AUTO) 4224 
SUBDESIGN dpram_1541
( 
	data[32..0]	:	input;
	inclock	:	input;
	outclock	:	input;
	outclocken	:	input;
	q[32..0]	:	output;
	rdaddress[6..0]	:	input;
	wraddress[6..0]	:	input;
	wren	:	input;
) 
VARIABLE 
	altsyncram6 : altsyncram_grh1;

BEGIN 
	altsyncram6.address_a[] = wraddress[];
	altsyncram6.address_b[] = rdaddress[];
	altsyncram6.clock0 = inclock;
	altsyncram6.clock1 = outclock;
	altsyncram6.clocken1 = outclocken;
	altsyncram6.data_a[] = data[];
	altsyncram6.wren_a = wren;
	q[] = altsyncram6.q_b[];
END;
--VALID FILE