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📄 a_graycounter_u16.tdf

📁 altera fpga 和ts201的linkport接口设计
💻 TDF
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--a_graycounter DEVICE_FAMILY="Stratix" WIDTH=7 aclr clock cnt_en q
--VERSION_BEGIN 11.1 cbx_a_gray2bin 2011:10:31:21:11:05:SJ cbx_a_graycounter 2011:10:31:21:11:05:SJ cbx_cycloneii 2011:10:31:21:11:05:SJ cbx_mgl 2011:10:31:21:12:31:SJ cbx_stratix 2011:10:31:21:11:05:SJ cbx_stratixii 2011:10:31:21:11:05:SJ  VERSION_END


-- Copyright (C) 1991-2011 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 10 
OPTIONS ALTERA_INTERNAL_OPTION = "{-to sub_parity4a0} POWER_UP_LEVEL=HIGH;{-to parity3} POWER_UP_LEVEL=LOW";

SUBDESIGN a_graycounter_u16
( 
	aclr	:	input;
	clock	:	input;
	cnt_en	:	input;
	q[6..0]	:	output;
) 
VARIABLE 
	counter5a[6..0] : dffeas;
	parity3 : dffeas
		WITH (
			power_up = "low"
		);
	sub_parity4a0 : dffeas
		WITH (
			power_up = "high"
		);
	sub_parity4a1 : dffeas;
	cntr_cout[6..0]	: WIRE;
	parity_cout	: WIRE;
	sclr	: NODE;
	updown	: NODE;

BEGIN 
	counter5a[].clk = clock;
	counter5a[].clrn = ( (! aclr), (! aclr), (! aclr), (! aclr), (! aclr), (! aclr), (! aclr));
	counter5a[].d = ( (counter5a[6].q $ cntr_cout[5..5]), (counter5a[5].q $ (counter5a[4].q & cntr_cout[4..4])), (counter5a[4].q $ (counter5a[3].q & cntr_cout[3..3])), (counter5a[3].q $ (counter5a[2].q & cntr_cout[2..2])), (counter5a[2].q $ (counter5a[1].q & cntr_cout[1..1])), (counter5a[1].q $ (counter5a[0].q & cntr_cout[0..0])), ((cnt_en & (counter5a[0].q $ (! parity_cout))) # ((! cnt_en) & counter5a[0].q)));
	counter5a[].sclr = sclr;
	parity3.clk = clock;
	parity3.clrn = (! aclr);
	parity3.d = ((cnt_en & (sub_parity4a[0..0].q $ sub_parity4a[1..1].q)) # ((! cnt_en) & parity3.q));
	parity3.sclr = sclr;
	sub_parity4a[1..0].clk = ( clock, clock);
	sub_parity4a[1].clrn = (! aclr);
	sub_parity4a[1..0].d = ( ((cnt_en & ((counter5a[4..4].q $ counter5a[5..5].q) $ counter5a[6..6].q)) # ((! cnt_en) & sub_parity4a[1].q)), ((cnt_en & (((counter5a[0..0].q $ counter5a[1..1].q) $ counter5a[2..2].q) $ counter5a[3..3].q)) # ((! cnt_en) & sub_parity4a[0].q)));
	sub_parity4a[0].prn = (! aclr);
	sub_parity4a[1..0].sclr = ( sclr, sclr);
	cntr_cout[] = ( B"0", (cntr_cout[4..4] & (! counter5a[4].q)), (cntr_cout[3..3] & (! counter5a[3].q)), (cntr_cout[2..2] & (! counter5a[2].q)), (cntr_cout[1..1] & (! counter5a[1].q)), (cntr_cout[0..0] & (! counter5a[0].q)), (cnt_en & parity_cout));
	parity_cout = ((parity3.q $ (! updown)) & cnt_en);
	q[] = counter5a[].q;
	sclr = GND;
	updown = VCC;
END;
--VALID FILE

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