📄 lp_rx_top_stratix.map.qmsg
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_gd9.tdf 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_gd9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_gd9 " "Info (12023): Found entity 1: dffpipe_gd9" { } { { "db/dffpipe_gd9.tdf" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/db/dffpipe_gd9.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_gd9 lp_rx:lp_rx\|dcfifo:rx_fifo\|dcfifo_0pm1:auto_generated\|alt_synch_pipe_mc8:dffpipe_rs_dgwp\|dffpipe_gd9:dffpipe9 " "Info (12128): Elaborating entity \"dffpipe_gd9\" for hierarchy \"lp_rx:lp_rx\|dcfifo:rx_fifo\|dcfifo_0pm1:auto_generated\|alt_synch_pipe_mc8:dffpipe_rs_dgwp\|dffpipe_gd9:dffpipe9\"" { } { { "db/alt_synch_pipe_mc8.tdf" "dffpipe9" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/db/alt_synch_pipe_mc8.tdf" 34 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_bvb.tdf 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_bvb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_bvb " "Info (12023): Found entity 1: add_sub_bvb" { } { { "db/add_sub_bvb.tdf" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/db/add_sub_bvb.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_bvb lp_rx:lp_rx\|dcfifo:rx_fifo\|dcfifo_0pm1:auto_generated\|add_sub_bvb:lpm_add_sub_rd_udwn " "Info (12128): Elaborating entity \"add_sub_bvb\" for hierarchy \"lp_rx:lp_rx\|dcfifo:rx_fifo\|dcfifo_0pm1:auto_generated\|add_sub_bvb:lpm_add_sub_rd_udwn\"" { } { { "db/dcfifo_0pm1.tdf" "lpm_add_sub_rd_udwn" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/db/dcfifo_0pm1.tdf" 72 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_cua.tdf 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_cua.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_cua " "Info (12023): Found entity 1: cntr_cua" { } { { "db/cntr_cua.tdf" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/db/cntr_cua.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_cua lp_rx:lp_rx\|dcfifo:rx_fifo\|dcfifo_0pm1:auto_generated\|cntr_cua:rdptr_b " "Info (12128): Elaborating entity \"cntr_cua\" for hierarchy \"lp_rx:lp_rx\|dcfifo:rx_fifo\|dcfifo_0pm1:auto_generated\|cntr_cua:rdptr_b\"" { } { { "db/dcfifo_0pm1.tdf" "rdptr_b" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/db/dcfifo_0pm1.tdf" 74 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "IMLS_MLS_DUP_REG_INFO_HDR" "" "Info (13005): Duplicate registers merged to single register" { } { } 0 13005 "Duplicate registers merged to single register" 0 0 "" 0 -1}
{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 speed 14 " "Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using \"speed\" technology mapper which leaves 14 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "" 0 -1}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info (18000): Registers with preset signals will power-up high" { } { { "../../../source/verilog/lp_rx.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/source/verilog/lp_rx.v" 51 -1 0 } } { "db/a_graycounter_u16.tdf" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/db/a_graycounter_u16.tdf" 37 2 0 } } { "../../../source/verilog/lp_rx.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/source/verilog/lp_rx.v" 398 -1 0 } } } 0 18000 "Registers with preset signals will power-up high" 0 0 "" 0 -1}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Info (16010): Generating hard_block partition \"hard_block:auto_generated_inst\"" { } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_NUMBER_VIRTUAL_IO" "37 " "Info (15717): Design contains 37 virtual pins; timing numbers associated with paths containing virtual pins are estimates" { { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rcser " "Info (15719): Pin \"rcser\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 28 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "empty " "Info (15719): Pin \"empty\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 34 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[0\] " "Info (15719): Pin \"rdata\[0\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[1\] " "Info (15719): Pin \"rdata\[1\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[2\] " "Info (15719): Pin \"rdata\[2\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[3\] " "Info (15719): Pin \"rdata\[3\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[4\] " "Info (15719): Pin \"rdata\[4\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[5\] " "Info (15719): Pin \"rdata\[5\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[6\] " "Info (15719): Pin \"rdata\[6\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[7\] " "Info (15719): Pin \"rdata\[7\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[8\] " "Info (15719): Pin \"rdata\[8\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[9\] " "Info (15719): Pin \"rdata\[9\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[10\] " "Info (15719): Pin \"rdata\[10\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[11\] " "Info (15719): Pin \"rdata\[11\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[12\] " "Info (15719): Pin \"rdata\[12\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[13\] " "Info (15719): Pin \"rdata\[13\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[14\] " "Info (15719): Pin \"rdata\[14\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[15\] " "Info (15719): Pin \"rdata\[15\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[16\] " "Info (15719): Pin \"rdata\[16\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[17\] " "Info (15719): Pin \"rdata\[17\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[18\] " "Info (15719): Pin \"rdata\[18\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[19\] " "Info (15719): Pin \"rdata\[19\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[20\] " "Info (15719): Pin \"rdata\[20\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[21\] " "Info (15719): Pin \"rdata\[21\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[22\] " "Info (15719): Pin \"rdata\[22\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[23\] " "Info (15719): Pin \"rdata\[23\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[24\] " "Info (15719): Pin \"rdata\[24\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[25\] " "Info (15719): Pin \"rdata\[25\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[26\] " "Info (15719): Pin \"rdata\[26\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[27\] " "Info (15719): Pin \"rdata\[27\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[28\] " "Info (15719): Pin \"rdata\[28\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[29\] " "Info (15719): Pin \"rdata\[29\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[30\] " "Info (15719): Pin \"rdata\[30\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[31\] " "Info (15719): Pin \"rdata\[31\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_OUTPUT" "rdata\[32\] " "Info (15719): Pin \"rdata\[32\]\" is virtual output pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 35 0 0 } } } 0 15719 "Pin \"%1!s!\" is virtual output pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "rdreq " "Info (15718): Pin \"rdreq\" is virtual input pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 33 0 0 } } } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} { "Info" "ICUT_CUT_VIRTUAL_INPUT" "rvere " "Info (15718): Pin \"rvere\" is virtual input pin" { } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 27 0 0 } } } 0 15718 "Pin \"%1!s!\" is virtual input pin" 0 0 "" 0 -1} } { } 0 15717 "Design contains %1!d! virtual pins; timing numbers associated with paths containing virtual pins are estimates" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "387 " "Info (21057): Implemented 387 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "9 " "Info (21058): Implemented 9 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Info (21059): Implemented 1 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "344 " "Info (21061): Implemented 344 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_RAMS" "33 " "Info (21064): Implemented 33 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "" 0 -1} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II 32-bit " "Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "467 " "Info: Peak virtual memory: 467 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 06 19:27:30 2012 " "Info: Processing ended: Fri Apr 06 19:27:30 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Info: Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
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