lp_rx_top_stratix.map.qmsg

altera fpga 和ts201的linkport接口设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Info: Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 11.1 Build 173 11/01/2011 SJ Full Version " "Info: Version 11.1 Build 173 11/01/2011 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 06 19:27:25 2012 " "Info: Processing started: Fri Apr 06 19:27:25 2012" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lp_rx_top_stratix -c lp_rx_top_stratix " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lp_rx_top_stratix -c lp_rx_top_stratix" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/fpga_test/ts201_altera/link_port-v1.1.0/source/verilog/lp_rx.v 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file /fpga_test/ts201_altera/link_port-v1.1.0/source/verilog/lp_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 lp_rx " "Info (12023): Found entity 1: lp_rx" {  } { { "../../../source/verilog/lp_rx.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/source/verilog/lp_rx.v" 25 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "lp_rx_top_stratix.v 1 1 " "Warning (12125): Using design file lp_rx_top_stratix.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lp_rx_top_stratix " "Info (12023): Found entity 1: lp_rx_top_stratix" {  } { { "lp_rx_top_stratix.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 2 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "lp_rx_top_stratix " "Info (12127): Elaborating entity \"lp_rx_top_stratix\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lp_rx lp_rx:lp_rx " "Info (12128): Elaborating entity \"lp_rx\" for hierarchy \"lp_rx:lp_rx\"" {  } { { "lp_rx_top_stratix.v" "lp_rx" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/lp_rx_top_stratix.v" 59 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "dr_sync4 lp_rx.v(201) " "Warning (10036): Verilog HDL or VHDL warning at lp_rx.v(201): object \"dr_sync4\" assigned a value but never read" {  } { { "../../../source/verilog/lp_rx.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/source/verilog/lp_rx.v" 201 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dcfifo lp_rx:lp_rx\|dcfifo:rx_fifo " "Info (12128): Elaborating entity \"dcfifo\" for hierarchy \"lp_rx:lp_rx\|dcfifo:rx_fifo\"" {  } { { "../../../source/verilog/lp_rx.v" "rx_fifo" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/source/verilog/lp_rx.v" 250 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "lp_rx:lp_rx\|dcfifo:rx_fifo " "Info (12130): Elaborated megafunction instantiation \"lp_rx:lp_rx\|dcfifo:rx_fifo\"" {  } { { "../../../source/verilog/lp_rx.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/source/verilog/lp_rx.v" 250 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lp_rx:lp_rx\|dcfifo:rx_fifo " "Info (12133): Instantiated megafunction \"lp_rx:lp_rx\|dcfifo:rx_fifo\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Stratix " "Info (12134): Parameter \"intended_device_family\" = \"Stratix\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 33 " "Info (12134): Parameter \"lpm_width\" = \"33\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 128 " "Info (12134): Parameter \"lpm_numwords\" = \"128\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 7 " "Info (12134): Parameter \"lpm_widthu\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clocks_are_synchronized FALSE " "Info (12134): Parameter \"clocks_are_synchronized\" = \"FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type dcfifo " "Info (12134): Parameter \"lpm_type\" = \"dcfifo\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Info (12134): Parameter \"lpm_showahead\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking ON " "Info (12134): Parameter \"overflow_checking\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking ON " "Info (12134): Parameter \"underflow_checking\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Info (12134): Parameter \"use_eab\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register OFF " "Info (12134): Parameter \"add_ram_output_register\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint RAM_BLOCK_TYPE=AUTO " "Info (12134): Parameter \"lpm_hint\" = \"RAM_BLOCK_TYPE=AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1}  } { { "../../../source/verilog/lp_rx.v" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/source/verilog/lp_rx.v" 250 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dcfifo_0pm1.tdf 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_0pm1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dcfifo_0pm1 " "Info (12023): Found entity 1: dcfifo_0pm1" {  } { { "db/dcfifo_0pm1.tdf" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/db/dcfifo_0pm1.tdf" 42 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dcfifo_0pm1 lp_rx:lp_rx\|dcfifo:rx_fifo\|dcfifo_0pm1:auto_generated " "Info (12128): Elaborating entity \"dcfifo_0pm1\" for hierarchy \"lp_rx:lp_rx\|dcfifo:rx_fifo\|dcfifo_0pm1:auto_generated\"" {  } { { "dcfifo.tdf" "auto_generated" { Text "e:/altera/11.1/quartus/libraries/megafunctions/dcfifo.tdf" 188 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_qec.tdf 1 1 " "Info (12021): Found 1 design units, including 1 entities, in source file db/a_fefifo_qec.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_qec " "Info (12023): Found entity 1: a_fefifo_qec" {  } { { "db/a_fefifo_qec.tdf" "" { Text "D:/FPGA_test/TS201_Altera/link_port-v1.1.0/build/lp_rx/stratix/db/a_fefifo_qec.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}